This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This allows to order the i2c devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 gpt is handled by the i.MX31 gpt driver in the kernel,
so add a corresponding compatible entry.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6Q and i.MX6DL are pin compatible, so the pinmux entries
should be in sync. This patch systematically adds the pinmux entries
missing from the imx6q to the imx6dl file.
Some name inconsistencies and whitespace damage is fixed along the
way.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch adds the missing (Keypad Port) KPP devicetree node
for i.MX27 CPUs.
Signed-off-by: NAlexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Define minimal memory layout for i.MX27 PCM-038 module.
This will help to use appended DTB with non-DT capable bootloaders.
Signed-off-by: NAlexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NAlexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

i.MX27 have only one PWM, so index from PWM devicetree node removed.
Signed-off-by: NAlexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch adds the missing (Digital Audio MUX) AUDMUX devicetree
node for i.MX27 CPUs.
Signed-off-by: NAlexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch adds the missing (Symmetric/Asymmetric Hashing and Random
Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.
Signed-off-by: NAlexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NPhilippe Reynes <tremyfr@yahoo.fr>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

enable the spi nor for imx6q{dl}-sabresd boards.
Signed-off-by: NHuang Shijie <b32955@freescale.com>

This new pinctrl is used by the imx6q-sabresd board.
Signed-off-by: NHuang Shijie <b32955@freescale.com>

This new pinctrl is used in the imx6dl-sabresd board.
Signed-off-by: NHuang Shijie <b32955@freescale.com>

It contains a bunch of imx soc updates for 3.12.

- Add more ethernet phy fixups for imx6 boards
- Add some missing imx6q clocks into clock driver
- Add new clock types fixup mux and div to work around some ugly
  hardware defect
- Consolidate L2 cache initialization function, so that it can be used
  on more i.MX SoCs
- Replace magic numbers in mach-imx6q.c with well defined macros
- Small fixes for imx6q and pllv3 clock drivers
- Some random updates on imx defconfig files

Add defines for common Micrel PHY setups so that other platforms
can use them. Update imx61 and sama5 hardware to use the micrel_phy.h
PHY defines.

Also add support for the KSZ9021RLRN PHY.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>
CC: Andrew Victor <linux@maxim.org.za>
CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: netdev@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Commit 02502da4 (ASoC: imx-mc13783: Depend on ARCH_ARM) caused the selection of
CONFIG_SND_SOC_IMX_MC13783 to be impossible due to a wrong dependency, which
caused CONFIG_SND_SOC_IMX_MC13783 to be removed after the defconfigs cleanups.

The original selection problem has been fixed by 9f19de64 (ASoC: imx-mc13783:
Make SND_SOC_IMX_MC13783 visible again), so it is possible to select
CONFIG_SND_SOC_IMX_MC13783 again as originally done.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Move anatop related (For USB) from board file to anatop driver
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Wandboard has a Broadcom 4329 chipset connected to SDHC, so turn on the wireless
related options.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Tested-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Generate imx_v4_v5_defconfig by doing:

make imx_v4_v5_defconfig
make savedefconfig
cp defconfig arch/arm/configs/imx_v4_v5_defconfig

No functional change. The goal here is to cleanup imx_v4_v5_defconfig file to
make easier and cleaner the addition of new entries.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Let SATA support be built by default.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Generate imx_v6_v7_defconfig by doing:

make savedefconfig

cp defconfig arch/arm/configs/imx_v6_v7_defconfig

No functional change. The goal here is to cleanup imx_v6_v7_defconfig file to
make easier and cleaner the addition of new entries.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Current imx53_pm_init() implementation is incomplete as it lacks calling
suspend_set_ops().

Use a single imx5_pm_init() function to handle both mx51 and mx53.

This allows mx53 to enter in low-power mode.

Tested on a mx53qsb:

root@freescale /$ echo mem > /sys/power/state
PM: Syncing filesystems ... done.
mmc0: card e624 removed
Freezing user space processes ... (elapsed 0.001 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
Suspending console(s) (use no_console_suspend to debug)

... (Press Power button)

PM: suspend of devices complete after 17.067 msecs
PM: suspend devices took 0.020 seconds
PM: late suspend of devices complete after 0.954 msecs
PM: noirq suspend of devices complete after 1.288 msecs
Disabling non-boot CPUs ...
PM: noirq resume of devices complete after 0.680 msecs
PM: early resume of devices complete after 0.914 msecs
PM: resume of devices complete after 44.955 msecs
PM: resume devices took 0.050 seconds
Restarting tasks ... done.
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SDHC card at address e624
mmcblk0: mmc0:e624 SU04G 3.69 GiB
 mmcblk0: p1 p2 p3
libphy: 63fec000.etherne:00 - Link is Down
libphy: 63fec000.etherne:00 - Link is Up - 100/Full
root@freescale /$
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Instead of selecting ARM_CPU_SUSPEND only for mx6, we can select it for
all SoCs from the ARCH_MXC family.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

egalax touchscren controller is present on mx6 sabresd/sabrelite, so let's
enable it by default.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the missing vdoa gate clock for imx6q.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and
there is a multiplexer to select between cko1 and cko2.  Add this
missing selection as the clock cko.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It adds the missing cko2 clocks, including multiplexer, divider and
gate.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It adds the missing spdif gate clock into imx6q clock driver.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There are two improvements for this commit:

- Add comparing pll lock condition after while loop. It can
fix potential fake timeout problem caused by the code is just
scheduled out before compare the timeout, and the time of
scheduling out are more than one jiffies.

- Move timeout assignment more close to compare the timeout.
It can reduce the possibility the code is scheduled out, and
the timeout can be more precise.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

All the clocks controlled by the register 'CCM Serial Clock
Multiplexer Register 1' should be fixup clocks. This patch
changes those clocks from basic multiplexer or divider clocks
to fixup clocks.
Signed-off-by: NLiu Ying <Ying.Liu@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>