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  1. 24 9月, 2010 1 次提交
    • S
      davinci: add support for aemif timing configuration · 8060ef4d
      由 Sekhar Nori 提交于 
      This patch adds support to configure the AEMIF interface
with supplied timing values.

Since this capability is useful both from NOR and NAND
flashes, it is provided as a new interface and in a file
of its own.

AEMIF timing configuration is required in cases:

1) Where the AEMIF clock rate can change at runtime (a side
   affect of cpu frequency change).

2) Where U-Boot does not support NAND/NOR but supports other
   media like SPI Flash or MMC/SD and thus does not care about
   setting up the AEMIF timing for kernel to use.

3) Where U-Boot just hasn't configured the timing values and
   cannot be upgraded because the box is already in the field.

Since there is now a header file for AEMIF interface, the
common (non-NAND specific) defines for AEMIF registers have
been moved from nand.h into the newly created aemif.h
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Acked-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      8060ef4d
  3. 13 9月, 2010 4 次提交
  5. 27 8月, 2010 1 次提交
  7. 21 8月, 2010 1 次提交
  9. 19 8月, 2010 1 次提交
  11. 18 8月, 2010 1 次提交
    • A
      pxa3xx: fix ns2cycle equation · 93b352fc
      由 Axel Lin 提交于 
      Test on a PXA310 platform with Samsung K9F2G08X0B NAND flash,
with tCH=5 and clk is 156MHz, ns2cycle(5, 156000000) returns -1.

ns2cycle returns negtive value will break NDTR0_tXX macros.

After checking the commit log, I found the problem is introduced by
commit 5b0d4d7c
"[MTD] [NAND] pxa3xx: convert from ns to clock ticks more accurately"

To get num of clock cycles, we use below equation:
num of clock cycles = time (ns) / one clock cycle (ns) + 1
We need to add 1 cycle here because integer division will truncate the result.
It is possible the developers set the Min values in SPEC for timing settings.
Thus the truncate may cause problem, and it is safe to add an extra cycle here.

The various fields in NDTR{01} are in units of clock ticks minus one,
thus we should subtract 1 cycle then.

Thus the correct equation should be:
num of clock cycles = time (ns) / one clock cycle (ns) + 1 - 1
                    = time (ns) / one clock cycle (ns)
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Signed-off-by: NLei Wen <leiwen@marvell.com>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
Cc: stable@kernel.org
      93b352fc
  13. 14 8月, 2010 1 次提交
  15. 12 8月, 2010 6 次提交
  17. 11 8月, 2010 6 次提交
  19. 09 8月, 2010 1 次提交
  21. 06 8月, 2010 17 次提交