1. 29 6月, 2012 21 次提交
    • A
      OMAPDSS: DISPC/APPLY: Use interlace info in manager timings for dispc_ovl_setup() · 8050cbe4
      Archit Taneja 提交于
      Currently the interlace parameter passed to dispc_ovl_setup() is configured by
      checking the display type, and set to true if the display type is VENC.
      
      This isn't correct as other panels can take interlaced content too. The
      omap_video_timings struct in manager's private data contains the info whether
      the panel is in interlaced mode or not.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      8050cbe4
    • A
      OMAPDSS: Add interlace parameter to omap_video_timings · 23c8f88e
      Archit Taneja 提交于
      Add a parameter called interlace which tells whether the timings are in
      interlaced or progressive mode. This aligns the omap_video_timings struct with
      the Xorg modeline configuration.
      
      It also removes the hack needed to write to divide the manager height by 2 if
      the connected interface is VENC.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      23c8f88e
    • A
      OMAPDSS: Remove omap_panel_config enum from omap_dss_device · 07fb51c6
      Archit Taneja 提交于
      omap_panel_config contains fields which are finally written to DISPC_POL_FREQo
      registers. These are now held by omap_video_timings and are set when the manager
      timings are applied.
      
      Remove the omap_panel_config enum, and remove all it's references from panel or
      interface drivers.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      07fb51c6
    • A
      OMAPFB: Map the newly added omap_video_timings fields with fb sync flags · 783babf3
      Archit Taneja 提交于
      Use the newly added fields in omap_video_timings(hsync, vsync and data_enable
      logic levels and data, hsync and vsync latching related info) to
      configure/retrieve corresponding sync flags in fb_var_screeninfo and
      fb_videomode.
      
      Out of the new fields, hsync_level and vsync_level can be mapped to the fb sync
      flags FB_SYNC_HOR_HIGH_ACT and FB_SYNC_VERT_HIGH_ACT.
      
      When converting fb mode to omap_video_timings, the fields which don't have an
      equivalent parameter in fb are kept as the original values if the panel driver
      has a get_timings op, else they are set to default values.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      783babf3
    • A
      OMAPDSS: DISPC: Remove dispc_mgr_set_pol_freq() · 0e065c79
      Archit Taneja 提交于
      dispc_mgr_set_pol_freq() configures the fields in the register DISPC_POL_FREQo.
      All these fields have been moved to omap_video_timings struct, and are now
      programmed in dispc_mgr_set_lcd_timings(). These will be configured when timings
      are applied via dss_mgr_set_timings().
      
      Remove dispc_mgr_set_pol_freq() and it's calls from the interface drivers.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      0e065c79
    • A
      OMAPDSS: DISPC: Configure newly added omap_video_timing fields · 655e2941
      Archit Taneja 提交于
      Hsync, Vsync, Data enable enable logic levels and latching info of Data lanes,
      Hsync and Vsync signals(with respect to pixel clock) are newly added parameters
      in omap_video_timings.
      
      Program these in dispc_mgr_set_lcd_timings. These will be configured when the
      manager's timings are set via dss_mgr_set_timings().
      Signed-off-by: NArchit Taneja <archit@ti.com>
      655e2941
    • A
      OMAPDSS: DISPLAY: Ignore newly added omap_video_timings fields for display timings sysfs file · a14909ea
      Archit Taneja 提交于
      The display sysfs file for viewing/storing display timings is something which
      will be deprecated. The new omap_video_timings fields (hsync_level, vsync_level
      and others) are not configurable or viewable via this sysfs file.
      
      This prevents the need to make the input more configurable to take the new
      fields and at the same time work without these fields for backward
      compatibility.
      
      In display_timings_store, the omap_video_timings struct used to set the timings
      is initialized to the existing panel timings so that the new fields are taken in
      correctly. The other fields are taken from the user as before.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      a14909ea
    • A
      OMAPDSS: Add some new fields to omap_video_timings · a8d5e41c
      Archit Taneja 提交于
      Some panel timing related fields are contained in omap_panel_config in the form
      of flags. The fields are:
      
      - Hsync logic level
      - Vsync logic level
      - Data driven on rising/falling edge of pixel clock
      - Output enable/Data enable logic level
      - HSYNC/VSYNC driven on rising/falling edge of pixel clock
      
      Out of these parameters, Hsync and Vsync logic levels are a part of the timings
      in the Xorg modeline configuration. So it makes sense to move the to
      omap_video_timings. The rest aren't a part of modeline, but it still makes
      sense to move these since they are related to panel timings.
      
      These fields stored in omap_panel_config in dssdev are configured for LCD
      panels, and the corresponding LCD managers in the DISPC_POL_FREQo registers.
      
      Add the above fields in omap_video_timings. Represent their state via new enums.
      
      Add these parameters to the omap_video_timings instances in the panel drivers.
      Keep the corresponding IVS, IHS, IPC, IEO, RF and ONOFF flags in
      omap_panel_config for now. The struct will be removed later.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      a8d5e41c
    • A
      OMAPDSS: Remove passive matrix LCD support (part 4) · a9105cb5
      Archit Taneja 提交于
      Remove configuration of Ac-bias pins
      
      Ac-bias pins need to be configured only for passive matrix displays. Remove
      acbi and acb fields in omap_dss_device and their configuration in panel
      drivers. Don't program these fields in DISP_POL_FREQo register any more.
      
      The panel driver for sharp-ls037v7dw01, and the panel config for
      Innolux AT070TN8 in generic dpi panel driver set acb to a non zero value. This
      is most likely carried over from the old omapfb driver which supported passive
      matrix displays.
      
      Cc: Thomas Weber <weber@corscience.de>
      Signed-off-by: NArchit Taneja <archit@ti.com>
      a9105cb5
    • A
      OMAPDSS: Remove passive matrix LCD support (part 3) · d21f43bc
      Archit Taneja 提交于
      Remove omap_lcd_display_type enum
      
      The enum omap_lcd_display_type is used to configure the lcd display type in
      DISPC. Remove this enum and always set display type to TFT by creating function
      dss_mgr_set_lcd_type_tft().
      Signed-off-by: NArchit Taneja <archit@ti.com>
      d21f43bc
    • A
      OMAPDSS: Remove passive matrix LCD support (part 2) · 5ae9eaa6
      Archit Taneja 提交于
      Remove OMAP_DSS_LCD_TFT as a omap_panel_config flag.
      
      We don't support passive matrix displays any more. Remove this flag from all the
      panel drivers.
      
      Force the display_type to OMAP_DSS_LCD_DISPLAY_TFT in the interface drivers.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      5ae9eaa6
    • A
      OMAPDSS: Remove passive matrix LCD support (part 1) · 6d523e7b
      Archit Taneja 提交于
      Remove clock constraints related to passive matrix displays.
      
      There is a constraint (pcd_min should be 3) for passive matrix displays. Remove
      this constraint in clock divider calculations as we won't support passive
      matrix displays any more.
      
      This cleans up the functions which calculate the clock dividers with DSI's PLL
      or DSS_FCLK as the clock source.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      6d523e7b
    • J
      OMAPDSS: HDMI: Replace spinlock with mutex in hdmi_check_hpd_state · 3a5383a2
      Jassi Brar 提交于
      State change of HDMI PHY could potentially take many millisecs, we can do
      better by protecting things in hdmi_set_phy_pwr() with a mutex rather than
      a spin_lock_irqsave.
      Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      3a5383a2
    • J
      OMAPDSS: HDMI: Discard phy_tx_enabled member · ece2f153
      Jassi Brar 提交于
      It is simpler to read the current status from a register as compared
      to maintaining a state variable to hold the information.
      Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      ece2f153
    • C
      OMAPDSS: Add dump and debug support for LCD3 · 6f1891fc
      Chandrabhanu Mahapatra 提交于
      DISPC functions have been modified to provide clock and register dumps and debug
      support for the LCD3 manager.
      Signed-off-by: NChandrabhanu Mahapatra <cmahapatra@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      6f1891fc
    • C
      OMAPDSS: Add LCD3 overlay manager and Clock and IRQ support · e86d456a
      Chandrabhanu Mahapatra 提交于
      The support for LCD3 manager has been added into the manager module. LCD3 panel
      has registers as DISPC_CONTROL3 and DISPC_CONFIG3 just like those in LCD and
      LCD2 panels. These registers control the Display Controller (DISPC) module for
      LCD3 output. The three LCDs support Display Serial Interface (DSI), Remote Frame
      Buffer Interface (RFBI) and Parallel CMOS Output Interface (DPI). These LCDs can
      be connected through parallel output interface using DISPC and RFBI or DPI. For
      serial interface DSS uses DSI.
      
      The LCD3 panel, just like LCD and LCD2 panels, has a clock switch in DSS_CTRL
      register which has been enabled. The clock switch chooses between DSS_CLK and
      DPLL_DSI1_C_CLK1 as source for LCD3_CLK. New IRQs as DISPC_IRQ_VSYNC3,
      DISPC_IRQ_FRAMEDONE3, DISPC_IRQ_ACBIAS_COUNT_STAT3 and DISPC_IRQ_SYNC_LOST3 have
      been added specific to the new manager.
      Signed-off-by: NChandrabhanu Mahapatra <cmahapatra@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      e86d456a
    • C
      OMAPDSS: Add support for LCD3 channel · ff6331e2
      Chandrabhanu Mahapatra 提交于
      OMAP5 Display Subsystem (DSS) architecture comes with a additional LCD3 channel
      with its own dedicated overlay manager. The current patch adds LCD3 channel and
      basic register support for LCD3 channel. It adds register addresses for various
      Display Controller (DISPC) registers like DISPC_DEFAULT_COLOR, DISPC_TIMING_H,
      DISPC_DIVISORo, etc.
      Signed-off-by: NChandrabhanu Mahapatra <cmahapatra@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      ff6331e2
    • C
      OMAPDSS: Cleanup implementation of LCD channels · efa70b3b
      Chandrabhanu Mahapatra 提交于
      The current implementation of LCD channels and managers consists of a number of
      if-else construct which has been replaced by a simpler interface. A constant
      structure mgr_desc has been created in Display Controller (DISPC) module. The
      mgr_desc contains for each channel its name, irqs and  is initialized one time
      with all registers and their corresponding fields to be written to enable
      various features of Display Subsystem. This structure is later used by various
      functions of DISPC which simplifies the further implementation of LCD channels
      and its corresponding managers.
      Signed-off-by: NChandrabhanu Mahapatra <cmahapatra@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      efa70b3b
    • T
      OMAPDSS: fix warnings if CONFIG_PM_RUNTIME=n · 5be3aebd
      Tomi Valkeinen 提交于
      If runtime PM is not enabled in the kernel config, pm_runtime_get_sync()
      will always return 1 and pm_runtime_put_sync() will always return
      -ENOSYS. pm_runtime_get_sync() returning 1 presents no problem to the
      driver, but -ENOSYS from pm_runtime_put_sync() causes the driver to
      print a warning.
      
      One option would be to ignore errors returned by pm_runtime_put_sync()
      totally, as they only say that the call was unable to put the hardware
      into suspend mode.
      
      However, I chose to ignore the returned -ENOSYS explicitly, and print a
      warning for other errors, as I think we should get notified if the HW
      failed to go to suspend properly.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Jassi Brar <jaswinder.singh@linaro.org>
      Cc: Grazvydas Ignotas <notasas@gmail.com>
      5be3aebd
    • T
      OMAPDSS: Use PM notifiers for system suspend · 2b8501d7
      Tomi Valkeinen 提交于
      The current way how omapdss handles system suspend and resume is that
      omapdss device (a platform device, which is not part of the device
      hierarchy of the DSS HW devices, like DISPC and DSI, or panels.) uses
      the suspend and resume callbacks from platform_driver to handle system
      suspend. It does this by disabling all enabled panels on suspend, and
      resuming the previously disabled panels on resume.
      
      This presents a few problems.
      
      One is that as omapdss device is not related to the panel devices or the
      DSS HW devices, there's no ordering in the suspend process. This means
      that suspend could be first ran for DSS HW devices and panels, and only
      then for omapdss device. Currently this is not a problem, as DSS HW
      devices and panels do not handle suspend.
      
      Another, more pressing problem, is that when suspending or resuming, the
      runtime PM functions return -EACCES as runtime PM is disabled during
      system suspend. This causes the driver to print warnings, and operations
      to fail as they think that they failed to bring up the HW.
      
      This patch changes the omapdss suspend handling to use PM notifiers,
      which are called before suspend and after resume. This way we have a
      normally functioning system when we are suspending and resuming the
      panels.
      
      This patch, I believe, creates a problem that somebody could enable or
      disable a panel between PM_SUSPEND_PREPARE and the system suspend, and
      similarly the other way around in resume. I choose to ignore the problem
      for now, as it sounds rather unlikely, and if it happens, it's not
      fatal.
      
      In the long run the system suspend handling of omapdss and panels should
      be thought out properly. The current approach feels rather hacky.
      Perhaps the panel drivers should handle system suspend, or the users of
      omapdss (omapfb, omapdrm) should handle system suspend.
      
      Note that after this patch we could probably revert
      0eaf9f52 (OMAPDSS: use sync versions of
      pm_runtime_put). But as I said, this patch may be temporary, so let's
      leave the sync version still in place.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Reported-by: NJassi Brar <jaswinder.singh@linaro.org>
      Tested-by: NJassi Brar <jaswinder.singh@linaro.org>
      2b8501d7
    • R
      OMAPDSS: add clk_prepare_enable and clk_disable_unprepare · f11766d1
      Rajendra Nayak 提交于
      In preparation of OMAP moving to Common Clk Framework(CCF) change
      clk_enable() and clk_disable() calls to clk_prepare_enable() and
      clk_disable_unprepare() in omapdss. This can be safely done, as omapdss
      never enables or disables clocks in atomic context.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: <linux-fbdev@vger.kernel.org>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      [tomi.valkeinen@ti.com: updated patch description]
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      f11766d1
  2. 28 6月, 2012 2 次提交
  3. 09 6月, 2012 1 次提交
    • L
      Revert "drm/i915/crt: Do not rely upon the HPD presence pin" · 8f53369b
      Linus Torvalds 提交于
      This reverts commit 9e612a00.
      
      It incorrectly finds VGA connectors where none are attached, apparently
      not noticing that nothing replied to the EDID queries, and happily using
      the default EDID modes that have nothing to do with actual hardware.
      
      That in turn then causes X to fall down to the lowest common
      denominator, which is usually the default 1024x768 mode that is in the
      default EDID and pretty much anything supports).
      
      I'd suggest that if not relying on the HDP pin, the code should at least
      check whether it gets valid EDID data back, rather than just assume
      there's something on the VGA connector.
      
      Cc: Dave Airlie <airlied@linux.ie>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      8f53369b
  4. 08 6月, 2012 1 次提交
  5. 07 6月, 2012 5 次提交
  6. 06 6月, 2012 2 次提交
  7. 05 6月, 2012 8 次提交