1. 09 9月, 2010 1 次提交
  2. 05 9月, 2010 1 次提交
  3. 26 8月, 2010 1 次提交
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      x86, tsc: Remove CPU frequency calibration on AMD · acf01734
      Borislav Petkov 提交于
      6b37f5a2 introduced the CPU frequency
      calibration code for AMD CPUs whose TSCs didn't increment with the
      core's P0 frequency. From F10h, revB onward, however, the TSC increment
      rate is denoted by MSRC001_0015[24] and when this bit is set (which
      should be done by the BIOS) the TSC increments with the P0 frequency
      so the calibration is not needed and booting can be a couple of mcecs
      faster on those machines.
      
      Besides, there should be virtually no machines out there which don't
      have this bit set, therefore this calibration can be safely removed. It
      is a shaky hack anyway since it assumes implicitly that the core is in
      P0 when BIOS hands off to the OS, which might not always be the case.
      Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <20100825162823.GE26438@aftab>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      acf01734
  4. 23 8月, 2010 5 次提交
  5. 22 8月, 2010 11 次提交
  6. 21 8月, 2010 21 次提交