- 13 1月, 2015 4 次提交
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由 Graham Moore 提交于
commit 3157d1ed ("mtd: denali: remove unnecessary casts") introduced an error by using a wrong bitmask. A uint16_t cast was replaced with & 0xff, should be & 0xffff. Signed-off-by: NGraham Moore <grmoore@opensource.altera.com> Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
drivers/mtd/devices/st_spi_fsm.c:1647:17: warning: comparison between signed and unsigned integer expressions Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
ST's Common Clk Framework is now available. This patch ensures the FSM makes use of it by obtaining and enabling the EMI clock. If system fails to provide the EMI clock, we bomb out. Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Under certain conditions, the SPI-FSM Controller can be left in a state where the data FIFO is not entirely empty. This can lead to problems where subsequent data transfers appear to have been shifted by a number of unidentified bytes. One simple example would be an errant FSM sequence which loaded more data to the FIFO than was read by the host. Another more interesting case results from an obscure artefact in the FSM Controller. When switching from data transfers in x4 or x2 mode to data transfers in x1 mode, extraneous bytes will appear in the FIFO, unless the previous data transfer was a multiple of 32 cycles (i.e. 8 bytes for x2, and 16 bytes for x4). This applies equally whether FSM is being operated directly by a S/W driver, or by the SPI boot-controller in FSM-Boot mode. Furthermore, data in the FIFO not only survive a transition between FSM-Boot and FSM, but also a S/W reset of IP block [1]. By taking certain precautions, it is possible to prevent the driver from causing this type of problem (e.g. ensuring that the host and programmed sequence agree on the transfer size, and restricting transfer sizes to multiples of 32-cycles [2]). However, at the point the driver is loaded, no assumptions can be made regarding the state of the FIFO. Even if previous S/W drivers have behaved correctly, it is impossible to control the number of transactions serviced by the controller operating in FSM-Boot. To address this problem, we ensure the FIFO is cleared during initialisation, before performing any FSM operations. Previously, the fsm_clear_fifo() code was capable of detecting and clearing any unwanted 32-bit words from the FIFO. This patch extends the capability to handle an arbitrary number of bytes present in the FIFO [3]. Now that the issue is better understood, we also remove the calls to fsm_clear_fifo() following the fsm_read() and fsm_write() operations. The process of actually clearing the FIFO deserves a mention. While the FIFO may contain any number of bytes, the SPI_FAST_SEQ_STA register only reports the number of complete 32-bit words present. Furthermore, data can only be drained from the FIFO by reading complete 32-bit words. With this in mind, a two stage process is used to the clear the FIFO: 1. Read any complete 32-bit words from the FIFO, as reported by the SPI_FAST_SEQ_STA register. 2. Mop up any remaining bytes. At this point, it is not known if there are 0, 1, 2, or 3 bytes in the FIFO. To handle all cases, a dummy FSM sequence is used to load one byte at a time, until a complete 32-bit word is formed; at most, 4 bytes will need to be loaded. [1] Although this issue has existed since early versions of the SPI-FSM controller, its full extent only emerged recently as a consequence of the targetpacks starting to use FSM-Boot(x4) as the default configuration. [2] The requirement to restrict transfers to multiples of 32 cycles was found empirically back when DUAL and QUAD mode support was added. The current analysis now gives a satisfactory explanation for this requirement. [3] Theoretically, it is possible for the FIFO to contain an arbitrary number of bits. However, since there are no known use-cases that leave incomplete bytes in the FIFO, only words and bytes are considered here. Signed-off-by: NAngus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 10 1月, 2015 5 次提交
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由 Aaron Sierra 提交于
UBI needs to know the physical erase block size, even on read-only devices, since it defines the on-device layout. Use a device-tree provided value to support previously written UBI on read-only NOR. UBI also needs a non-zero writebufsize, so we set it to one. Note: This was implemented because hardware write-protected CFI NOR cannot be probed for the physical erase block size. Signed-off-by: NJoe Schultz <jschultz@xes-inc.ccom> Signed-off-by: NAaron Sierra <asierra@xes-inc.ccom> [Brian: removed unneeded #ifdef, note 'optional' erase-size property] Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Joe Schultz 提交于
Previously, when probing a CFI chip which was write-protected at the hardware level, the probe would fail due to the fact it could not put the chip into QUERY mode. This would result in no MTD devices being created. Add a fallback to probe using the map_rom driver if the user-selected probe fails. Signed-off-by: NJoe Schultz <jschultz@xes-inc.com> Signed-off-by: NAaron Sierra <asierra@xes-inc.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Alessio Igor Bogani 提交于
Signed-off-by: NAlessio Igor Bogani <alessio.bogani@elettra.eu> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Andy Shevchenko 提交于
We need to compare ret variable for negative value. The current code assigns the boolean to the ret and prints it wrongly in the warning message. Reported-by: NAndrey Karpov <karpov@viva64.com> Cc: Giel van Schijndel <me@mortis.eu> Cc: Dimitri Gorokhovik <dimitri.gorokhovik@free.fr> Signed-off-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Baruch Siach 提交于
Commit 7854d3f7 ("mtd: spelling, capitalization, uniformity") added a correctly spelled line, but failed to remove the wrongly spelled one. Commit 064a7694 ("mtd: Fix typo mtd/tests") then fixed the spelling again, but left the duplication. Fixes: 7854d3f7 ("mtd: spelling, capitalization, uniformity") Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 08 1月, 2015 7 次提交
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由 Scott Branden 提交于
Add nand_shutdown to wait for current nand operations to finish and prevent further operations by changing the nand flash state to FL_SHUTDOWN. This is addressing a problem observed during reboot tests using UBIFS root file system: NAND erase operations that are in progress during system reboot/shutdown are causing partial erased blocks. Although UBI should be able to detect and recover from this error, this change will avoid the creation of partial erased blocks on reboot in the middle of a NAND erase operation. Signed-off-by: NScott Branden <sbranden@broadcom.com> Tested-by: NScott Branden <sbranden@broadcom.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Brian Norris 提交于
cfi_cmdset_000{1,2}.c already implement their own reboot notifiers, and we're going to add one for NAND. Let's put the boilerplate in one place. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Tested-by: NScott Branden <sbranden@broadcom.com>
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由 Gu Zheng 提交于
The global lock mtdblks_lock was used to protect the original mtdblks array to avoid race conditions. As the mtdblks array was already gone, but the mtdblks_lock is left, and it causes latency when open/release dev. So we need to remove it here. Signed-off-by: NGu Zheng <guz.fnst@cn.fujitsu.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
SquashFS is supposed to use magic defined as SQUASHFS_MAGIC. What we were supporting so far (SQSH_MAGIC) is something ZTE specific. This patch adds support for Xiaomi R1D. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
Some devices like Netgear WNR1000v3 or WGR614v10 have partitions aligned to 0x1000. Using bigger blocksize stopped us from detecting some parts. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Bean Huo 霍斌斌 (beanhuo) 提交于
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR (Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command. There is no difference between these two methods. Unfortunately, for some Micron SPI NOR flashes, there no ENTER Quad I/O command (35h), such as n25q064. But for all current Micron SPI NOR, if it support quad I/O mode, using EVCR definitely be supported. It is a recommended method to enable Quad I/O mode by EVCR, Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate in quad I/O mode. This patch has been tested on N25Q512A and MT25TL256BAA1ESF. Micron SPI NOR of spi_nor_ids[] table all support this method. Signed-off-by: NBean Huo <beanhuo@micron.com> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 23 12月, 2014 2 次提交
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由 Boris BREZILLON 提交于
Now that we have raw functions properly implemented we can remove this FIXME. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NHuang Shijie <shijie.huang@intel.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Fabio Estevam 提交于
mx28evk board has a socket for NAND flash that comes with no NAND flash populated, and then we get this message on every boot: [ 1.657603] gpmi-nand 8000c000.gpmi-nand: driver registration failed: -19 which is not very helpful, so get rid of this error message. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 13 12月, 2014 2 次提交
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由 Brian Norris 提交于
The torture test should quit once it actually induces an error in the flash. This step was accidentally removed during refactoring. Without this fix, the torturetest just continues infinitely, or until the maximum cycle count is reached. e.g.: ... [ 7619.218171] mtd_test: error -5 while erasing EB 100 [ 7619.297981] mtd_test: error -5 while erasing EB 100 [ 7619.377953] mtd_test: error -5 while erasing EB 100 [ 7619.457998] mtd_test: error -5 while erasing EB 100 [ 7619.537990] mtd_test: error -5 while erasing EB 100 ... Fixes: 6cf78358 ("mtd: mtd_torturetest: use mtd_test helpers") Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: Akinobu Mita <akinobu.mita@gmail.com> Cc: <stable@vger.kernel.org>
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由 Ard Biesheuvel 提交于
On device remove, when testing the cmtd field of an of_flash struct to decide whether it is a concatenated device or not, we get a false positive on cmtd == NULL, and dereference it subsequently. This may occur if of_flash_remove() is called from the cleanup path of of_flash_probe(). Instead, test for NULL first, and only then perform the test for a concatenated device. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 02 12月, 2014 1 次提交
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由 Rafał Miłecki 提交于
This will allow spi-nor users to plainly use JEDEC to detect flash chip. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 01 12月, 2014 7 次提交
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由 Boris BREZILLON 提交于
Implement raw OOB access functions to retrieve OOB bytes when accessing the NAND in raw mode. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Tested-by: NHuang Shijie <shijie8@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Boris BREZILLON 提交于
Several MTD users (either in user or kernel space) expect a valid raw access support to NAND chip devices. This is particularly true for testing tools which are often touching the data stored in a NAND chip in raw mode to artificially generate errors. The GPMI drivers do not implemenent raw access functions, and thus rely on default HW_ECC scheme implementation. The default implementation consider the data and OOB area as properly separated in their respective NAND section, which is not true for the GPMI controller. In this driver/controller some OOB data are stored at the beginning of the NAND data area (these data are called metadata in the driver), then ECC bytes are interleaved with data chunk (which is similar to the HW_ECC_SYNDROME scheme), and eventually the remaining bytes are used as OOB data. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Tested-by: NHuang Shijie <shijie8@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Boris BREZILLON 提交于
Add a new function to copy bits (not bytes) from a memory region to another one. This function is similar to memcpy except it acts at bit level. It is needed to implement GPMI raw access functions and adapt to the hardware ECC engine which does not pad ECC bits to the next byte boundary. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Tested-by: NHuang Shijie <shijie8@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Brian Norris 提交于
write_enable() was being duplicated to both m25p80.c and fsl-quadspi.c. But this should be handled within the spi-nor abstraction layer. At the same time, let's add write_disable() after erasing, so we don't leave the flash in a write-enabled state afterward. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NHuang Shijie <shijie.huang@intel.com>
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由 Huang Shijie 提交于
We need to store the six bytes ID for s25fl128s, since it shares the same five bytes with s25fl129p1. This patch adds a macro INFO6 which is used for the six bytes ID flash, and adds a new item for the s25fl128s. Signed-off-by: NHuang Shijie <shijie.huang@intel.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Huang Shijie 提交于
The "id" array contains all the information about the JEDEC and the manufacturer ID info. This patch removes the jedec_id/ext_id from flash_info. Signed-off-by: NHuang Shijie <shijie.huang@intel.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Huang Shijie 提交于
This patch adds the id/id_len fields for flash_info{}, and rewrite the INFO to fill them. And at last, we read out 6 bytes in the spi_nor_read_id(), and we use these new fields to parse out the correct flash_info. Signed-off-by: NHuang Shijie <shijie.huang@intel.com> Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 29 11月, 2014 1 次提交
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由 Gu Zheng 提交于
Signed-off-by: NGu Zheng <guz.fnst@cn.fujitsu.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 26 11月, 2014 9 次提交
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由 Wu, Josh 提交于
There is no need to use memcpy32_toio/memcpy32_fromio to transfer data between memory and NFC sram. As the NFC sram is a also a memory space not an I/O space, we can just use memcpy(). We remove the __iomem prefix for NFC sram to avoid sparse warnings. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Reviewed-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Brian Norris 提交于
This write_page() function is functionally equivalent to the default in nand_base.c. Its only difference is in subpage programming support, which cafe_nand.c does not advertise, so the difference is negligible. Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Knut Wohlrab 提交于
Signed-off-by: NKnut Wohlrab <knut.wohlrab@de.bosch.com> Signed-off-by: NAlison Chaiken <alison_chaiken@mentor.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Alison Chaiken 提交于
As stated in a5b7616c, "mtd: m25p80,spi-nor: Fix module aliases for m25p80", m25p_ids[] in m25p80.c needs to be kept in sync with spi_nor_ids[] in spi-nor.c. The change here corrects a misalignment. (We were missing m25px80 and we had a duplicate w25q128.) Signed-off-by: NAlison Chaiken <alison_chaiken@mentor.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: <stable@vger.kernel.org> # 3.18+
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由 Brian Norris 提交于
There are a few small issues with the timeout loop in spi_nor_wait_till_ready(): * The first operation should not be a reschedule; we should check the status register at least once to see if we're complete! * We should check the status register one last time after declaring the deadline has passed, to prevent a premature timeout error (this is theoretically possible if we sleep for a long time after the previous status register check). * Add an error message, so it's obvious if we ever hit a timeout. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NHuang Shijie <shijie.huang@intel.com> Reviewed-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
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由 Markus Elfring 提交于
The functions kfree() and pci_dev_put() test whether their argument is NULL and then return immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Roger Quadros 提交于
3430LDP has NAND flash with 32 bytes OOB size which is sufficient to hold BCH8 codes but the small page check introduced in commit b491da72 ("mtd: nand: omap: clean-up ecc layout for BCH ecc schemes") considers anything below 64 bytes unsuitable for BCH4/8/16. There is another bug in that code where it doesn't skip the check for OMAP_ECC_HAM1_CODE_SW. Get rid of that small page check code as it is insufficient and redundant because we are checking for OOB available bytes vs ecc layout before calling nand_scan_tail(). Fixes: b491da72 ("mtd: nand: omap: clean-up ecc layout for BCH ecc schemes") Reported-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Brian Norris 提交于
Tested with ATO AFND1G08U3, 128MiB NAND. Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
It may be useful info, e.g. if someone wants to use ubinize. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 20 11月, 2014 2 次提交
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由 Brian Norris 提交于
Fixes warning: drivers/mtd/tests/oobtest.c: In function 'memcmpshow': drivers/mtd/tests/oobtest.c:129: warning: format '%x' expects type 'unsigned int', but argument 3 has type 'size_t' Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Cc: Roger Quadros <rogerq@ti.com> Cc: Sekhar Nori <nsekhar@ti.com>
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由 Roger Quadros 提交于
It is common for NAND devices to have bitflip errors. Add a bitflip_limit parameter to specify how many bitflips per page we can tolerate without flagging an error. By default zero bitflips are tolerated. Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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