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  1. 14 3月, 2016 1 次提交
  3. 10 3月, 2016 1 次提交
  5. 08 3月, 2016 6 次提交
  7. 05 3月, 2016 17 次提交
  9. 01 3月, 2016 1 次提交
  11. 26 2月, 2016 9 次提交
    • S
      drm/fsl-dcu: fix register initialization · f76b9873
      由 Stefan Agner 提交于 
      The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
Vybrid) whereas the register enumeration start from 1 (1-10 for
LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
iterations and initialized the number of layers inclusive, which
is one layer too many.

All extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      f76b9873
    • S
      drm/fsl-dcu: use mode flags for hsync/vsync polarity · 4bc390c6
      由 Stefan Agner 提交于 
      The current default configuration is as follows:
- Invert VSYNC signal (active LOW)
- Invert HSYNC signal (active LOW)

The mode flags allow to specify the required polarity per
mode. Furthermore, none of the current driver settings is
actually a standard polarity.

This patch applies the current driver default polarities as
explicit flags to the display which has been introduced with
the driver (NEC WQVGA "nec,nl4827hc19-05b"). The driver now
also parses the flags field and applies the configuration
accordingly, by using the following values as standard
polarities: (e.g. when no flags are specified):
- VSYNC signal not inverted (active HIGH)
- HSYNC signal not inverted (active HIGH)
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
      4bc390c6
    • S
      drm/fsl-dcu: fix alpha blending · 69855819
      由 Stefan Agner 提交于 
      Fix alpha blending by enabling alpha blending for the whole frame if
a color mode with alpha channel is selected (DRM_FORMAT_ARGB*). Also
support color modes without alpha channel (DRM_FORMAT_XRGB*) by just
not enabling alpha blending on layer level.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      69855819
    • S
      drm/fsl-dcu: mask all interrupts on initialization · 638c93f6
      由 Stefan Agner 提交于 
      The state of the interrupt mask register on initialization is
unknown, e.g. U-Boot could already used the DCU. So depending on
the boot loader, the outcome of the interrupt mask register could
be different. A defined state is much more preferable. Also, there
is no value in keeping interrupts enabled which we don't need.
Therefor, mask all interrupts on initialization.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      638c93f6
    • S
      drm/fsl-dcu: handle initialization errors properly · 7566e247
      由 Stefan Agner 提交于 
      If initialization fails (e.g. due to missing panel node or deferred
probe) make sure to roll-back all operations and return the error
code.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      7566e247
    • S
      drm/fsl-dcu: avoid memory leak on errors · 72cc05a5
      由 Stefan Agner 提交于 
      Improve error handling during CRTC initialization. Especially avoid
memory leaks in the primary plane initialization error path.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      72cc05a5
    • S
      drm/fsl-dcu: remove regmap return value checks · e291d298
      由 Stefan Agner 提交于 
      It is not common to do regmap return value checks, especially not
for memory mapped device. We can rule out most error returns since
the conditions are static and we know they are ok (e.g. offset
aligned to register stride). Also without proper error handling
they are not really valuable for the user. Hence remove most of
them.

The check in the interrupt handler is worth keeping since a
volatile register won't be readable in case register caching is
still enabled.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      e291d298
    • S
      drm/fsl-dcu: specify volatile registers · efb8b491
      由 Stefan Agner 提交于 
      Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      efb8b491
    • M
      drm: fsl-dcu: Fix no fb check bug · a36c9867
      由 Meng Yi 提交于 
      For state->fb or state->crtc may be NULL in fsl_dcu_drm_plane_atomic_check
function, if so, return 0.
Signed-off-by: NMeng Yi <meng.yi@nxp.com>
Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
      a36c9867
  13. 23 2月, 2016 5 次提交