dmaengine device should explicitly call devm_free_irq() when using
devm_request_irq().

The irq is still ON when devices remove is executed and irq should be
quiesced before remove is completed.
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This patch updates the dmatest client to
Support scatter-gather dma mode.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Currently the handler ignores the channel 0 interrupt and thus doesn't ack
it properly. This is done in order to allow sdma_run_channel0() to poll
on the irq status bit, as this function may be called in atomic context,
but needs to know when the channel has finished.

This works mostly, as the polling happens under a spinlock, disabling IRQs
on the local CPU, leaving only a very slight race window for a spurious
IRQ to happen if the handler is executed on another CPU in an SMP system.
Still this is clearly suboptimal.
This behavior turns into a real problem on an RT system, where the spinlock
doesn't disable IRQs on the local CPU. Not acking the IRQ in the handler
in such a setup is very likely to drown the CPU in an IRQ storm, leaving
it unable to make any progress in the polling loop, leading to the IRQ
never being acked.

Fix this by properly acknowledging the channel 0 IRQ in the handler.
As the IRQ status bit can no longer be used to poll for the channel
completion, switch over to using the SDMA_H_STATSTOP register for this
purpose, where bit 0 is cleared by the hardware when the channel is done.
Signed-off-by: NMichael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

In case of error, the function platform_device_register_full()
returns ERR_PTR() and never returns NULL. The NULL test in the
return value check should be replaced with IS_ERR().
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The new mv_xor_v2 driver supports the XOR engines found in the 64-bits
ARM from Marvell of the Armada 7K and Armada 8K family. This XOR
engine is a completely new hardware block, entirely different from the
one used on previous Marvell Armada platforms, which use the existing
mv_xor driver.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This commit adds the Device Tree binding documentation for the Marvell
XOR v2 engine, which is found on Marvell Armada 7K/8K ARM64 SoCs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The newly added zynqmp_dma driver produces a warning on 32-bit architectures
when dma_addr_t is 64-bit wide:

drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_config_sg_ll_desc':
drivers/dma/xilinx/zynqmp_dma.c:321:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
        ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v);
         ^
drivers/dma/xilinx/zynqmp_dma.c:321:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
        ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v);

This changes the cast to the more appropriate uintptr_t.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

In cyclic DMA mode need to link the tail bd segment
with the head bd segment to process bd's in cyclic.

Current driver is doing this only for tx channel
needs to update the same for rx channel case also.

This patch fixes the same.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and I/O to I/O buffer transfers.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Device-tree binding documentation for Xilinx zynqmp dma engine
used in Zynq UltraScale+ MPSoC.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NPunnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Cookies corresponding to pending transfers have a residue value equal to
the full size of the corresponding descriptor. The driver miscomputes
that and uses the size of the active descriptor instead. Fix it.
Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[geert: Also check desc.active list]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Running descriptor pointer is set to NULL upon freeing resources. Other-
wise, rcar_dmac_issue_pending might not start new transfers
Signed-off-by: NMuhammad Hamza Farooq <mfarooq@visteon.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The documentation states one should make sure both DE and TE are cleared
before starting a transaction. This patch extends the current warning to
look at both DE and TE.

Based on previous work from Muhammad Hamza Farooq.
Suggested-by: NMuhammad Hamza Farooq <mfarooq@visteon.com>
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The hardware might have complete the transfer but the interrupt handler
might not have had a chance to run. If rcar_dmac_chan_get_residue()
which reads HW registers finds that there is no residue return
DMA_COMPLETE.
Signed-off-by: NMuhammad Hamza Farooq <mfarooq@visteon.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
[Niklas: add explanation in commit message]
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Current driver assumes that child node channel name is either
"xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel"
which is confusing the users of AXI DMA and CDMA.
This patch fixes this issue by using different channel
names for the AXI DMA and AXI CDMA child nodes.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

In the existing vdma driver support for
AXI DMA and CDMA got added so the driver is no
longer VDMA specific.

This patch renames the driver and DT binding doc to xilinx_dma
and updates the Kconfig description for all the DMAS.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The AXI DMA support is added to the existing AXI VDMA
driver. Device tree binding information also updated
in the VDMA binding doc.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This patch adds support for AXI DMA multi-channel dma mode
Multichannel mode enables DMA to connect to multiple masters
and slaves on the streaming side.

In Multichannel mode AXI DMA supports 2D transfers.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This patch updates the device-tree binding doc for
AXI DMA multi channel dma mode.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The bam_dma driver gained runtime PM support, but that causes build
warnings whenever CONFIG_PM is disabled:

drivers/dma/qcom/bam_dma.c:1324:12: error: 'bam_dma_runtime_resume' defined but not used [-Werror=unused-function]
 static int bam_dma_runtime_resume(struct device *dev)
            ^~~~~~~~~~~~~~~~~~~~~~
drivers/dma/qcom/bam_dma.c:1315:12: error: 'bam_dma_runtime_suspend' defined but not used [-Werror=unused-function]
 static int bam_dma_runtime_suspend(struct device *dev)

This removes the incomplete #ifdef guard and instead marks all
four PM functions as __maybe_unused, which avoids this kind of
warning.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 7d254559 ("dmaengine: qcom-bam-dma: Add pm_runtime support")
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

When building this driver on arm64, we get a harmless type
mismatch warning:

drivers/dma/bcm2835-dma.c: In function 'bcm2835_dma_fill_cb_chain_with_sg':
include/linux/kernel.h:743:17: warning: comparison of distinct pointer types lacks a cast
  (void) (&_min1 == &_min2);  \
                 ^
drivers/dma/bcm2835-dma.c:409:21: note: in expansion of macro 'min'
    cb->cb->length = min(len, max_len);

This changes the type of the 'len' variable to size_t, which
avoids the problem.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 388cc7a2 ("dmaengine: bcm2835: add slave_sg support to bcm2835-dma")
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Return IRQ_NONE in the interrupt handler when it is called but no IRQs are
pending. This allows the system to recover in case of an interrupt storm
e.g. due to a wrong interrupt configuration setup.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Propagate errors returned by platform_get_irq() to the driver core. This
will enable proper probe deferring for the driver in case the IRQ provider
has not been registered yet.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Add MODULE_DEVICE_TABLE() for the axi-dmac driver. This allows the driver
to be loaded on demand when built as a module.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

When building this driver on arm64, we get a harmless type
mismatch warning:

drivers/dma/bcm2835-dma.c: In function 'bcm2835_dma_fill_cb_chain_with_sg':
include/linux/kernel.h:743:17: warning: comparison of distinct pointer types lacks a cast
  (void) (&_min1 == &_min2);  \
                 ^
drivers/dma/bcm2835-dma.c:409:21: note: in expansion of macro 'min'
    cb->cb->length = min(len, max_len);

This changes the type of the 'len' variable to size_t, which
avoids the problem.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 388cc7a2 ("dmaengine: bcm2835: add slave_sg support to bcm2835-dma")
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Adds pm_runtime support for BAM DMA so that clock is enabled only
when there is a transaction going on to help save power.
Signed-off-by: NPramod Gurav <pramod.gurav@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Commit 71f7e6cc ('dmaengine: tegra20-apb-dma: Only calculate residue
if txstate exists') changed the tegra_dma_tx_status() function to only
calculate the residue if there is a valid 'txstate' pointer for storing
the residue. Although this makes sense, this changed the behaviour of
the function tegra_dma_tx_status() such that if the pointer 'txstate' is
not valid, then we will return whatever state is returned by
dma_cookie_status() and no longer return the state by looking up the DMA
descriptor and returning it's state.

Please note that dma_cookie_status() will either return DMA_COMPLETE or
DMA_IN_PROGRESS. However, if dma_cookie_status() returns DMA_IN_PROGRESS
the actual status could be DMA_ERROR which will only be seen from
checking the descriptor status. Therefore, even if 'txstate' is not
valid, still check to see if there is a valid descriptor for the cookie
in question and if so return the descriptor state. Finally, ensure the
residue is still not calculated if the 'txstate' is not valid.
Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>