1. 16 5月, 2014 1 次提交
    • T
      genirq: Provide generic hwirq allocation facility · 7b6ef126
      Thomas Gleixner 提交于
      Not really the solution to the problem, but at least it confines the
      mess in the core code and allows to get rid of the create/destroy_irq
      variants from hell, i.e. 3 implementations with different semantics
      plus the x86 specific variants __create_irqs and create_irq_nr
      which have been invented in another circle of hell.
      
      x86 : x86 should be converted to irq domains and I'm deliberately
            making it impossible to do the multi-vector MSI support by
            adding more crap to the current mess. It's not that hard to do
            and I'm really tired of the trainwrecks which have been invented
            by baindaid engineering so far. Any attempt to do multi-vector
            MSI or ioapic hotplug without converting to irq domains is NAKed
            hereby.
      
      tile: Might use irq domains as well, but it has a very limited
            interrupt space, so handling it via this functionality might be
            the right thing to do even in the long run.
      
      ia64: That's an hopeless case, as I doubt that anyone has the stomach
            to rewrite the homebrewn dynamic allocation facilities. I stared
            at it for a couple of hours and gave up. The create/destroy_irq
            mess could be made private to itanic right away if there
            wouldn't be the iommu/dmar driver being shared with x86. So to
            do that I'm going to add a separate ia64 specific implementation
            later in order not to deep-six itanic right away.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NGrant Likely <grant.likely@linaro.org>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: Fenghua Yu <fenghua.yu@intel.com>
      Cc: x86@kernel.org
      Link: http://lkml.kernel.org/r/20140507154334.208629358@linutronix.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      7b6ef126
  2. 05 2月, 2014 1 次提交
  3. 13 9月, 2013 1 次提交
  4. 11 4月, 2012 1 次提交
  5. 30 3月, 2012 1 次提交
  6. 26 1月, 2012 1 次提交
    • R
      irq: make SPARSE_IRQ an optionally hidden option · 2ed86b16
      Rob Herring 提交于
      On ARM, we don't want SPARSE_IRQ to be a user visible option. Make
      SPARSE_IRQ visible based on MAY_HAVE_SPARSE_IRQ instead of depending
      on HAVE_SPARSE_IRQ.
      
      With this, SPARSE_IRQ is not visible on C6X and ARM.
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Aurelien Jacquiot <a-jacquiot@ti.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-c6x-dev@linux-c6x.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: linux-sh@vger.kernel.org
      2ed86b16
  7. 28 7月, 2011 1 次提交
    • G
      irq: add irq_domain translation infrastructure · 08a543ad
      Grant Likely 提交于
      This patch adds irq_domain infrastructure for translating from
      hardware irq numbers to linux irqs.  This is particularly important
      for architectures adding device tree support because the current
      implementation (excluding PowerPC and SPARC) cannot handle
      translation for more than a single interrupt controller.  irq_domain
      supports device tree translation for any number of interrupt
      controllers.
      
      This patch converts x86, Microblaze, ARM and MIPS to use irq_domain
      for device tree irq translation.  x86 is untested beyond compiling it,
      irq_domain is enabled for MIPS and Microblaze, but the old behaviour is
      preserved until the core code is modified to actually register an
      irq_domain yet.  On ARM it works and is required for much of the new
      ARM device tree board support.
      
      PowerPC has /not/ been converted to use this new infrastructure.  It
      is still missing some features before it can replace the virq
      infrastructure already in powerpc (see documentation on
      irq_domain_map/unmap for details).  Followup patches will add the
      missing pieces and migrate PowerPC to use irq_domain.
      
      SPARC has its own method of managing interrupts from the device tree
      and is unaffected by this change.
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      08a543ad
  8. 03 5月, 2011 1 次提交
  9. 30 3月, 2011 1 次提交
  10. 29 3月, 2011 1 次提交
  11. 28 3月, 2011 1 次提交
  12. 26 3月, 2011 1 次提交
  13. 09 3月, 2011 1 次提交
  14. 26 2月, 2011 1 次提交
    • T
      genirq: Provide forced interrupt threading · 8d32a307
      Thomas Gleixner 提交于
      Add a commandline parameter "threadirqs" which forces all interrupts except
      those marked IRQF_NO_THREAD to run threaded. That's mostly a debug option to
      allow retrieving better debug data from crashing interrupt handlers. If
      "threadirqs" is not enabled on the kernel command line, then there is no
      impact in the interrupt hotpath.
      
      Architecture code needs to select CONFIG_IRQ_FORCED_THREADING after
      marking the interrupts which cant be threaded IRQF_NO_THREAD. All
      interrupts which have IRQF_TIMER set are implict marked
      IRQF_NO_THREAD. Also all PER_CPU interrupts are excluded.
      
      Forced threading hard interrupts also forces all soft interrupt
      handling into thread context.
      
      When enabled it might slow down things a bit, but for debugging problems in
      interrupt code it's a reasonable penalty as it does not immediately
      crash and burn the machine when an interrupt handler is buggy.
      
      Some test results on a Core2Duo machine:
      
      Cache cold run of:
       # time git grep irq_desc
      
            non-threaded       threaded
       real 1m18.741s          1m19.061s
       user 0m1.874s           0m1.757s
       sys  0m5.843s           0m5.427s
      
       # iperf -c server
      non-threaded
      [  3]  0.0-10.0 sec  1.09 GBytes   933 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   934 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   933 Mbits/sec
      threaded
      [  3]  0.0-10.0 sec  1.09 GBytes   939 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   934 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   937 Mbits/sec
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      LKML-Reference: <20110223234956.772668648@linutronix.de>
      8d32a307
  15. 23 2月, 2011 1 次提交
  16. 19 2月, 2011 4 次提交
  17. 21 1月, 2011 1 次提交
  18. 12 10月, 2010 1 次提交
  19. 04 10月, 2010 2 次提交