Stoney is SMC 8.x.
Signed-off-by: NSamuel Li <samuel.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The logic was reversed.  This feature is not enabled
at the moment, but fix it now for the future.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

VCE, UVD DPM work similarly to SCLK DPM.  Report the current
clock levels for UVD and VCE via debugfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

CZ uses a different set of registers compared to previous asics
and supports separate NB and GFX planes.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

So the selected forced level shows up properly in sysfs.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This is necessary to properly reset the min/max limits before
clamping them otherwise we may get improper clamping depending
on what what was the last forced level.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes a hang on resume.
Signed-off-by: NSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Enable VCE dpm and powergating. VCE dpm dynamically scales the VCE clocks on
demand.
Signed-off-by: NSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

smu_init allocates buffers and initializes them.  It does not
touch the hw.  There is no need to do it again on resume.  It
should really be part of sw_init (and smu_fini should be part
of sw_fini), but we need the firmware sizes from the other IPs
for firmware loading so we have to wait until sw init is done
for all other IPs.
Reviewed-by: NSonny Jiang <Sonny.Jiang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The structure is renamed and moved to amd_shared.h to make
the component independent.  This makes it easier to add
new components in the future.

v2: fix include path
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Nyanyang1 <young.yang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable UVD dpm (dynamic power management) and powergating.  UVD dpm dynamically scales the UVD
clocks on demand.  Powergating turns off the power to the block when it's not in use.
Signed-off-by: NSonny Jiang <sonny.jiang@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Fix crash when disabling dpm.

v2: agd5f: fix coding style, cleanup commit message
Signed-off-by: NSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Need to unlock the mutex on error.
Noticed-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds initial support for VI asics.  This
includes Iceland, Tonga, and Carrizo.  Our inital
focus as been Carrizo, so there are still gaps in
support for Tonga and Iceland, notably power
management.
Acked-by: NChristian König <christian.koenig@amd.com>
Acked-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>