1. 23 6月, 2017 3 次提交
  2. 06 6月, 2017 2 次提交
  3. 20 4月, 2017 7 次提交
  4. 11 4月, 2017 5 次提交
  5. 07 2月, 2017 1 次提交
    • J
      iwlwifi: mvm/pcie: adjust A-MSDU tx_cmd length in PCIe · 05e5a7e5
      Johannes Berg 提交于
      Instead of setting the tx_cmd length in the mvm code, which is
      complicated by the fact that DQA may want to temporarily store
      the SKB on the side, adjust the length in the PCIe code which
      also knows about this since it's responsible for duplicating
      all those headers that are account for in this code.
      
      As the PCIe code already relies on the tx_cmd->len field, this
      doesn't really introduce any new dependencies.
      
      To make this possible we need to move the memcpy() of the TX
      command until after it was updated.
      
      This does even simplify the code though, since the PCIe code
      already does a lot of manipulations to build A-MSDUs correctly
      and changing the length becomes a simple operation to see how
      much was added/removed, rather than predicting it.
      
      Fixes: 24afba76 ("iwlwifi: mvm: support bss dynamic alloc/dealloc of queues")
      Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      05e5a7e5
  6. 04 12月, 2016 1 次提交
  7. 19 10月, 2016 1 次提交
  8. 23 9月, 2016 1 次提交
  9. 19 9月, 2016 1 次提交
  10. 16 9月, 2016 5 次提交
  11. 30 8月, 2016 1 次提交
  12. 06 7月, 2016 6 次提交
  13. 11 5月, 2016 2 次提交
  14. 30 3月, 2016 1 次提交
    • S
      iwlwifi: pcie: do not pad QoS AMSDU · c772a3d3
      Sara Sharon 提交于
      We insert padding if the MAC header's size is not a multiple of 4
      to ensure that the SNAP header is DWORD aligned. When we do so, we
      let the firmware know by setting a bit in Tx command
      (TX_CMD_FLG_MH_PAD) which will instruct the firmware to drop those
      2 bytes before sending the frame.
      However, this is not needed for AMSDU as the sub frame header (14B)
      complements the MAC header (26B) so that the SNAP header is DWORD
      aligned without adding any pad.
      
      Until 9000, the firmware didn't check the TX_CMD_FLG_MH_PAD bit
      but rather checked the length of the MAC header itself and
      assumed the entity that enqueued the frame (driver or internal
      firmware code) added the pad.
      Since the driver inserted the pad even for AMSDU this logic applied.
      Note that the padding is a DMA optimization but it's not strictly
      needed, so we could pad even if it was not needed.
      
      However, the CSUM hardware introduced for the 9000 devices requires
      to not pad AMSDU as it is not needed, and will fail if such a pad
      exists.
      Due to older FW not checking the padding bit but checking the mac
      header size itself - we cannot do this adjustments for older
      generations.
      Do not align the size if it is an AMSDU and HW checksum is enabled -
      which will only happen on 9000 devices and on.
      Signed-off-by: NSara Sharon <sara.sharon@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      c772a3d3
  15. 20 3月, 2016 1 次提交
  16. 28 2月, 2016 1 次提交
  17. 01 2月, 2016 1 次提交