1. 13 10月, 2007 1 次提交
  2. 12 10月, 2007 1 次提交
  3. 11 10月, 2007 1 次提交
    • N
      pxamci: support arbitrary block size · c783837b
      Nicolas Pitre 提交于
      The PXA has two transmit FIFOes, each32 byte deep.  when one FIFO is
      full and the other one has been transmitted, they are automatically
      swapped and DMA is triggered for another 32 byte burst.  However, when
      there is less than 32 bytes left to send, the FIFO swap has to be done
      manually. This is required for some SDIO transfers which are not
      required to be multiples of 32 bytes.
      
      A DMA completion interrupt is set for each descriptor which length isn't
      a multiple of 32 in order to force the FIFO swap.  While at it, the DMA
      interrupt handler has been made a bit more resilient against errors.
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
      c783837b
  4. 06 10月, 2007 2 次提交
  5. 04 10月, 2007 5 次提交
  6. 27 9月, 2007 1 次提交
    • P
      sdio: adaptive interrupt polling · 6f4285d1
      Pierre Ossman 提交于
      The interrupt polling frequency is a compromise between power usage and
      interrupt latency. Unfortunately, it affects throughput rather severely
      for devices which require an interrupt for every chunk of data.
      
      By making the polling frequency adaptive, we get better throughput with
      those devices without sacficing too much power. Polling will quickly
      increase when there is an actual interrupt, and slowly fall back to the
      idle frequency when the interrupts stop coming.
      Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
      6f4285d1
  7. 26 9月, 2007 4 次提交
  8. 25 9月, 2007 1 次提交
  9. 24 9月, 2007 24 次提交