- 20 4月, 2017 1 次提交
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由 Sara Sharon 提交于
In a000 transport we will allocate queues dynamically. Right now queue are allocated as one big chunk of memory and accessed as such. The dynamic allocation of the queues will require accessing the queues as pointers. In order to keep simplicity of pre-a000 tx queues handling, keep allocating and freeing the memory in the same style, but move to access the queues in the various functions as individual pointers. Dynamic allocation for the a000 devices will be in a separate patch. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 11 4月, 2017 2 次提交
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由 Sara Sharon 提交于
Context information structure is going to be used in a000 devices for firmware self init. The self init includes firmware self loading from DRAM by ROM. This means the TFH relevant firmware loading can be cleaned up. The firmware loading includes the paging memory as well, so op mode can stop initializing the paging and sending the DRAM_BLOCK_CMD. Firmware is doing RFH, TFH and SCD configuration, while driver only fills the required configurations and addresses in the context information structure. The only remaining access to RFH is the write pointer, which is updated upon alive interrupt after FW configured the RFH. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Emmanuel Grumbach 提交于
We don't need to print so much data in the kernel log. Limit the data to be printed to the queue that actually got stuck in case of a TFD queue hang, and stop dumping all the CSR and FH registers. Over the course of time, the CSR and FH values haven't proven themselves to be really useful for debugging, and they are now in the firmware dump anyway. This comes as a preparation to the addition of more data required to be printed by the firwmare team. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 08 2月, 2017 1 次提交
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由 Golan Ben Ami 提交于
Currently, when getting a RFKILL interrupt, the transport enters a flow in which it stops the device, disables other interrupts, etc. After stopping the device, the transport resets the hw, and sleeps. During the sleep, a context switch occurs and host commands are sent by upper layers (e.g. mvm) to the fw. This is possible since the op_mode layer and the transport layer hold different mutexes. Since the STATUS_RFKILL bit isn't set, the transport layer doesn't recognize that RFKILL was toggled on, and no commands can actually be sent, so it enqueues the command to the tx queue and sets a timer on the queue. After switching context back to stopping the device, STATUS_RFKILL is set, and then the transport can't send the command to the fw. This eventually results in a queue hang. Fix this by setting STATUS_RFKILL immediately when the interrupt is fired. Signed-off-by: NGolan Ben-Ami <golan.ben.ami@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 07 2月, 2017 1 次提交
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由 Johannes Berg 提交于
When resuming, it's possible for the following scenario to occur: * iwl_pci_resume() enables the RF-kill interrupt * iwl_pci_resume() reads the RF-kill state (e.g. to 'radio enabled') * RF_KILL interrupt triggers, and iwl_pcie_irq_handler() reads the state, now 'radio disabled', and acquires the &trans_pcie->mutex. * iwl_pcie_irq_handler() further calls iwl_trans_pcie_rf_kill() to indicate to the higher layers that the radio is now disabled (and stops the device while at it) * iwl_pcie_irq_handler() drops the mutex * iwl_pci_resume() continues, acquires the mutex and calls the higher layers to indicate that the radio is enabled. At this point, the device is stopped but the higher layers think it's available, and can call deeply into the driver to try to enable it. However, this will fail since the device is actually disabled. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 19 9月, 2016 2 次提交
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由 Johannes Berg 提交于
There's no need to declare a list and then init it manually, just use the LIST_HEAD() macro. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
Log group as well. Remove 0x prefix to match TX logging. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 16 9月, 2016 2 次提交
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由 Haim Dreyfuss 提交于
In case the OS provides fewer interrupts than requested, different causes will share the same interrupt vector as follow: 1.One interrupt less: non rx causes shared with FBQ. 2.Two interrupts less: non rx causes shared with FBQ and RSS. 3.More than two interrupts: we will use fewer RSS queues. Also make the request depend on the number of online CPUs instead of possible CPUs. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
The original intent was to have the general iwl_queue shared between RX and TX queues, but it is not the actual status. Since it is not shared with any struct but iwl_txq, it adds unnecessary complexity. Merge those structs. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 06 7月, 2016 6 次提交
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由 Sara Sharon 提交于
Move the write_prph_64 of pcie to be transport agnostic. Add direct write as well, as it is needed for a000 HW. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
In MQ environment and new architecture in early stages we may encounter DMA issues. Track RXB status and bail out in case we receive index to an RXB that was not mapped and handed over to HW. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Emmanuel Grumbach 提交于
Upon firmware load interrupt (FH_TX), the ISR re-enables the firmware load interrupt only to avoid races with other flows as described in the commit below. When the firmware is completely loaded, the thread that is loading the firmware will enable all the interrupts to make sure that the driver gets the ALIVE interrupt. The problem with that is that the thread that is loading the firmware is actually racing against the ISR and we can get to the following situation: CPU0 CPU1 iwl_pcie_load_given_ucode ... iwl_pcie_load_firmware_chunk wait_for_interrupt <interrupt> ISR handles CSR_INT_BIT_FH_TX ISR wakes up the thread on CPU0 /* enable all the interrupts * to get the ALIVE interrupt */ iwl_enable_interrupts ISR re-enables CSR_INT_BIT_FH_TX only /* start the firmware */ iwl_write32(trans, CSR_RESET, 0); BUG! ALIVE interrupt will never arrive since it has been masked by CPU1. In order to fix that, change the ISR to first check if STATUS_INT_ENABLED is set. If so, re-enable all the interrupts. If STATUS_INT_ENABLED is clear, then we can check what specific interrupt happened and re-enable only that specific interrupt (RFKILL or FH_TX). All the credit for the analysis goes to Kirtika who did the actual debugging work. Cc: <stable@vger.kernel.org> [4.5+] Fixes: a6bd005f ("iwlwifi: pcie: fix RF-Kill vs. firmware load race") Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
In cases of hardware or DMA error, the vid read from a zeroed location will be 0, and we will access the rxb at index 0 in the global table, while it may be NULL or owned by hardware. Invalidate vid 0 in order to detect the situation and bail out. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
Somehow we ended up stopping RX using legacy RX registers even for devices that support RFH. Fix it. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
Currently code calls restock for mq devices during the init function, unlike sq where restock is called after init. This causes an harmless but alarming deadlock warning from lockdep, to fix this - unify the init code. Rename the restock functions while at it. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 01 7月, 2016 4 次提交
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由 Sara Sharon 提交于
Add a warning in case packet didn't end up in the HW destined queue. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
We now have 9000 devices that support multiple frames in a single RB. Enable it. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
For 9000 devices we can have PCIe bus for discrete devices and IOSF bus for integrated devices. PCIe supports maximum transfer size of 128B while IOSF bus supports maximum transfer size of 64B. Configure RB size accordingly. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
Integrated 9000 devices have a bug with shadow registers value retention. If driver writes RBD registers while MAC is asleep the values are stored in shadow registers to be copied whenever MAC wakes up. However, in 9000 devices a MAC wakeup is not triggered and when the bus powers down due to inactivity the shadow values and dirty bits are lost. Turn on the chicken-bits that cause MAC wakeup for RX-related values as well when the device is in D0. When the device is in low power mode turn the RX wakeup chicken bits off since driver is idle and this W/A is not needed. Remove previous W/A which was ineffective. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 11 5月, 2016 3 次提交
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由 Sara Sharon 提交于
When initializing RX we grab NIC access for every read and write. This is redundant - we can just grab access once. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Sara Sharon 提交于
The RX queues have a shadow register for the write pointer that enables updates without grabbing NIC access. Use them instead of the periphery registers because accessing those is much more expensive. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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由 Haim Dreyfuss 提交于
CSR registers are always available even when the NIC is not awake, no need to wake up the NIC before accessing them. This has a huge impact when we re-enable an interrupt at the end of the ISR since waking up the NIC can take some time. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
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- 30 3月, 2016 3 次提交
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由 Colin Ian King 提交于
isr_stats is written twice with the same value, remove one of the redundant assignments to isr_stats. Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Sara Sharon 提交于
Due to hardware bug, upon any shadow free-queue register write access, a legacy RBD shadow register must be written as well. This is required in order to trigger a copy of the shadow registers values after MAC exits sleep state. Specifically, the driver has to write (any value) to the legacy RBD register each time FRBDCB is accessed. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Sara Sharon 提交于
My patch resized the pool size, but neglected to resize the global table, which is obviously wrong since the global table maps the pool's rxb to vid one to one. This results in a panic in 9000 devices. Add a build bug to avoid such a case in the future. Fixes: 7b542436 ("iwlwifi: pcie: fine tune number of rxbs") Reported-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 10 3月, 2016 2 次提交
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由 Gregory Greenman 提交于
When trying to reach high Rx throughput of more than 500Mbps on a device with a relatively weak CPU (Atom x5-Z8500), CPU utilization may become a bottleneck. Analysis showed that we are looping in iwl_pcie_rx_handle for very long periods which led to starvation of other threads (iwl_pcie_rx_handle runs with _bh disabled). We were handling Rx and allocating new buffers and the new buffers were ready quickly enough to be available before we had finished handling all the buffers available in the hardware. As a consequence, we called iwl_pcie_rxq_restock to refill the hardware with the new buffers, and start again handling new buffers without exiting the function. Since we read the hardware pointer again when we goto restart, new buffers were handled immediately instead of exiting the function. This patch avoids refilling RBs inside rx handling loop, unless an emergency situation is reached. It also doesn't read the hardware pointer again unless we are in an emergency (unlikely) case. This significantly reduce the maximal time we spend in iwl_pcie_rx_handle with _bh disabled. Signed-off-by: NGregory Greenman <gregory.greenman@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Sara Sharon 提交于
We kick the allocator when we have 2 RBDs that don't have attached RBs, and the allocator allocates 8 RBs meaning that it needs another 6 RBDs to attach the RBs to. The design is that allocator should always have enough RBDs to fulfill requests, so we give in advance 6 RBDs to the allocator so that when it is kicked, it gets additional 2 RBDs and has enough RBDs. These RBDs were taken from the Rx queue itself, meaning that each Rx queue didn't have the maximal number of RBDs, but MAX - 6. Change initial number of RBDs in the system to include both queue size and allocator reserves. Note the multi-queue is always 511 instead of 512 to avoid a full queue since we cannot detect this state easily enough in the 9000 arch. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 07 3月, 2016 2 次提交
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由 Sara Sharon 提交于
128 byte chunk size is supported only on PCIe and not on IOSF. For now, change it back to 64 byte. Reported-by: NOren Givon <oren.givon@intel.com> Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Sara Sharon 提交于
Change the code to move rxbs directly from the allocator's list to the queue's free list. This makes the code more readable, saves the interim array and the double loop over the free RBs. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 02 3月, 2016 1 次提交
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由 Sara Sharon 提交于
In 9000 series A0 step the closed_rb_num is not wrapping around properly. The queue is wrapping around as it should, so we can W/A it by wrapping the closed_rb_num in the driver. While at it, extend RX logging and add error handling of other cases HW values may cause us to access invalid memory locations. Add also a proper masking of vid value read from HW - this should not have actual affect, but better to be on the safe side. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 28 2月, 2016 2 次提交
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由 Sara Sharon 提交于
Fine tune RFH registers further: * Set default queue explicitly * Set RFH to drop frames exceeding RB size * Set the maximum rx transfer size to DRAM to 128 instead of 64 Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Haim Dreyfuss 提交于
Working with MSIX requires prior configuration. This includes requesting interrupt vectors from the OS, registering the vectors and mapping the optional causes to the relevant interrupt. In addition add new interrupt handler to handle MSIX interrupt. Signed-off-by: NHaim Dreyfuss <haim.dreyfuss@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 15 2月, 2016 1 次提交
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由 Emmanuel Grumbach 提交于
When we load the firmware, we hold trans_pcie->mutex to avoid nested flows. We also rely on the ISR to wake up the thread when the DMA has finished copying a chunk. During this flow, we enable the RF-Kill interrupt. The problem is that the RF-Kill interrupt handler can take the mutex and bring the device down. This means that if we load the firmware while the RF-Kill switch is enabled (which will happen when we load the INIT firmware to read the device's capabilities and register to mac80211), we may get an RF-Kill interrupt immediately and the ISR will be waiting for the mutex held by the thread that is currently loading the firmware. At this stage, the ISR won't be able to service the DMA's interrupt needed to wake up the thread that load the firmware. We are in a deadlock situation which ends when the thread that loads the firmware fails on timeout and releases the mutex. To fix this, take the mutex later in the flow, disable the interrupts and synchronize_irq() to give a chance to the RF-Kill interrupt to run and complete. After that, mask all the interrupts besides the DMA interrupt and proceed with firmware load. Make sure to check that there was no RF-Kill interrupt when the interrupts were disabled. This fixes https://bugzilla.kernel.org/show_bug.cgi?id=111361Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 01 2月, 2016 1 次提交
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由 Sara Sharon 提交于
Previous patches enabled new 9000 hardware DMA for one queue only. Enable the actual multi-queue path and configuration now. This requires also per-queue NAPI struct. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 31 1月, 2016 2 次提交
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由 Sara Sharon 提交于
The 9000 series introduces several changes in the device DMA operation. As the device now supports multi-queue rx, several DMA channels should be configured. The flows of providing the device with the allocated RBDs now changes as well - the device maintains a separate table of used and free table. The hardware may use the free table to feed RBDs to any queue. This requires maintaing a shared table to map returned RBDs to the original RXB - for that purpose the VID is introduced - an internal identifier of the RB placed in the lower 12 bits and returned by HW in the used data. Another change is the support of 64 bit DMA address. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Sara Sharon 提交于
The 9000 series devices will support multi rx queues. Current code has one static rx queue - change it to allocate a number of queues per the device capability (pre-9000 devices have the number of rx queues set to one). Subsequent generalizations are: Change the code to access an explicit numbered rx queue only when the queue number is known - when handling interrupt, when accessing the default queue and when iterating the queues. The rest of the functions will receive the rx queue as a pointer. Generalize the warning in allocation failure to consider the allocator status instead of a single rx queue status. Move the rx initial pool of memory buffers to be shared among all the queues and allocated to the default queue on init. Signed-off-by: NSara Sharon <sara.sharon@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 13 12月, 2015 1 次提交
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由 Sharon Dvir 提交于
Host commands now have a group id, express this in printed messages. Signed-off-by: NSharon Dvir <sharon.dvir@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 02 12月, 2015 2 次提交
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由 Emmanuel Grumbach 提交于
ilw@linux.intel.com is not available anymore. linuxwifi@intel.com should be used instead. Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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由 Johannes Berg 提交于
Since this pointer is not shown anywhere else, it's useless. Remove it, just keeping the indexes. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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- 26 11月, 2015 1 次提交
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由 Johannes Berg 提交于
This message isn't very useful and presents a security risk due to the use of %p - remove it. Signed-off-by: NJohannes Berg <johannes.berg@intel.com> Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
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