- 14 2月, 2015 13 次提交
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由 Damien Lespiau 提交于
This W/A is put in a gen9 specific function because it may well be needed on other gen9 platforms. Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Let's also take the opportunity the remove the comment telling it's a pre-prod W/A, it should be obvious from the stepping test. Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
We'll gather cross-gen9 W/A in a separate function later. Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NNick Hoath <nicholas.hoath@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Yu Zhang 提交于
With Intel GVT-g, GPU power management is controlled by host driver, so there is no need to provide virtualized GPU PM support. In the future it might be useful to gather VM input for freq boost, but now let's disable it simply. v2: take Chris' comments: - do not special case this to gen6+ Signed-off-by: NYu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: NJike Song <jike.song@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
When enabling new platforms, we may not have any W/A to apply, especially that, now, a bunch of them have to be done from the ring. Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Hoath, Nicholas 提交于
Move Wa4x4STCOptimizationDisable to gen9_init_workarounds v2: rebase Signed-off-by: NNick Hoath <nicholas.hoath@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Hoath, Nicholas 提交于
v2: Add stepping check for WaDisableSDEUnitClockGating. Signed-off-by: NNick Hoath <nicholas.hoath@intel.com> Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> [danvet: Rebase.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Nick Hoath 提交于
Move WaDisableDgMirrorFixInHalfSliceChicken5 to gen9_init_workarounds v2: Added stepping check v3: Removed unused register bitmap Signed-off-by: NNick Hoath <nicholas.hoath@intel.com> [danvet: Bikesheds.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Replace the valleyview_set_rps() and gen6_set_rps() calls with intel_set_rps() which itself does the IS_VALLEYVIEW() check. The code becomes simpler since the callers don't have to do this check themselves. Most of the change was performe with the following semantic patch: @@ expression E1, E2, E3; @@ - if (IS_VALLEYVIEW(E1)) { - valleyview_set_rps(E2, E3); - } else { - gen6_set_rps(E2, E3); - } + intel_set_rps(E2, E3); Adding intel_set_rps() and making valleyview_set_rps() and gen6_set_rps() static was done manually. Also valleyview_set_rps() had to be moved a bit avoid a forward declaration. v2: Use a less greedy semantic patch Cc: Chris Wilson <chris@chris-wilson.co.uk> Suggested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 31 1月, 2015 1 次提交
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由 Ville Syrjälä 提交于
Move the CHV check into vlv_set_rps_idle() to simplify the caller a bit. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 27 1月, 2015 16 次提交
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由 Ville Syrjälä 提交于
Replace all the vlv_gpu_freq(), vlv_freq_opcode(), *GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances with intel_gpu_freq() and intel_freq_opcode() calls. Most of the change was performed with the following semantic patch: @@ expression E; @@ ( - E * GT_FREQUENCY_MULTIPLIER + intel_gpu_freq(dev_priv, E) | - E *= GT_FREQUENCY_MULTIPLIER + E = intel_gpu_freq(dev_priv, E) | - E /= GT_FREQUENCY_MULTIPLIER + E = intel_freq_opcode(dev_priv, E) | - do_div(E, GT_FREQUENCY_MULTIPLIER) + E = intel_freq_opcode(dev_priv, E) ) @@ expression E1, E2; @@ ( - vlv_gpu_freq(E1, E2) + intel_gpu_freq(E1, E2) | - vlv_freq_opcode(E1, E2) + intel_freq_opcode(E1, E2) ) @@ expression E1, E2, E3, E4; @@ ( - if (IS_VALLEYVIEW(E1)) { - E2 = intel_gpu_freq(E3, E4); - } else { - E2 = intel_gpu_freq(E3, E4); - } + E2 = intel_gpu_freq(E3, E4); | - if (IS_VALLEYVIEW(E1)) { - E2 = intel_freq_opcode(E3, E4); - } else { - E2 = intel_freq_opcode(E3, E4); - } + E2 = intel_freq_opcode(E3, E4); ) One hunk was manually undone as intel_gpu_freq() ended up calling itself. Supposedly it would be possible to exclude certain functions via !=~, but I couldn't get that to work. Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat wrappers was done manually. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Rename the vlv_gpu_freq() and vlv_freq_opecode() functions to have an intel_ prefix, and handle non-VLV/CHV platforms in them as well. Leave the vlv_ names around for now since they're currently used. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
We set the WIZ hashing mode to 16x4 for all the other gen6+ platfotrms, so let's follow suit on VLV. My VLV is AWOL currently so I didn't test this, but since the results for all the other platforms agree that 16x4 is the fastest we might assume the same holds for VLV. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NArun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Drop WaDisablePwrmtrEvent:chv as it's no longer needed. Also remove the WaSetMaskForGfxBusyness:chv note, but we still leave the GEN6_RP_MEDIA_IS_GFX bit enabled as that's still the recommended setting. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NArun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Zhe Wang 提交于
Enable coarse power gating for Gen9. This feature allows render and media engine to enter RC6 independently. Policies are configured together with RC6. This feature will only be enabled when RC6 is enabled. v2: Rebase after Chris'/Mika's forcewake change (Damien) Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NZhe Wang <zhe1.wang@intel.com> Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Damien Lespiau 提交于
v2: Use the new function, gen6_init_rps_frequencies() (Damien) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (v1) Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jesse Barnes 提交于
Per latest PM programming guide. v2: the wrong flavour of the function updating the ring frequency was called, leading to dead locks (Tvrtko) v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien) Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDamien Lespiau <damien.lespiau@intel.com> Reviewed-by: NMika Kuoppala <mika.kuoppala@intel.com> [danvet: Fixup conflicts with Mika's forcewake refactor.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Mika Kuoppala 提交于
We have multiple forcewake domains now on recent gens. Change the function naming to reflect this. v2: More verbose names (Chris) v3: Rebase v4: Rebase v5: Add documentation for forcewake_get/put Signed-off-by: NMika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> (v2) Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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To match the semantics of drm_crtc->state, which this will eventually become. The allocation of the memory for config will be fixed in a followup patch. By adding the extra _config field to intel_crtc it was possible to generate this entire patch with the cocci script below. @@ @@ struct intel_crtc { ... -struct intel_crtc_state config; +struct intel_crtc_state _config; +struct intel_crtc_state *config; ... } @@ struct intel_crtc *crtc; @@ -memset(&crtc->config, 0, sizeof(crtc->config)); +memset(crtc->config, 0, sizeof(*crtc->config)); @@ @@ __intel_set_mode(...) { <... -to_intel_crtc(crtc)->config = *pipe_config; +(*(to_intel_crtc(crtc)->config)) = *pipe_config; ...> } @@ @@ intel_crtc_init(...) { ... WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); +intel_crtc->config = &intel_crtc->_config; return; ... } @@ struct intel_crtc *crtc; @@ -&crtc->config +crtc->config @@ struct intel_crtc *crtc; identifier member; @@ -crtc->config.member +crtc->config->member @@ expression E; @@ -&(to_intel_crtc(E)->config) +to_intel_crtc(E)->config @@ expression E; identifier member; @@ -to_intel_crtc(E)->config.member +to_intel_crtc(E)->config->member v2: Clarify manual changes by splitting them into another patch. (Matt) Improve cocci script to generate even more of the changes. (Ander) Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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And get rid of the duplicate mode structures. This patch was generated with the following semantic patch: @@ @@ struct intel_crtc_state { +struct drm_crtc_state base; + ... -struct drm_display_mode requested_mode; -struct drm_display_mode adjusted_mode; ... } @@ struct intel_crtc_state *state; @@ -state->adjusted_mode +state->base.adjusted_mode @@ struct intel_crtc_state *state; @@ -state->requested_mode +state->base.mode @@ struct intel_crtc_state state; @@ -state.adjusted_mode +state.base.adjusted_mode @@ struct intel_crtc_state state; @@ -state.requested_mode +state.base.mode @@ struct drm_crtc *crtc; @@ -to_intel_crtc(crtc)->config.adjusted_mode +to_intel_crtc(crtc)->config.base.adjusted_mode @@ identifier member; expression E; @@ -PIPE_CONF_CHECK_FLAGS(adjusted_mode.member, E); +PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.member, E); @@ identifier member; @@ -PIPE_CONF_CHECK_I(adjusted_mode.member); +PIPE_CONF_CHECK_I(base.adjusted_mode.member); @@ identifier member; @@ -PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.member); +PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.member); v2: Completely generate the patch with cocci. (Ander) Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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The objective is to make this structure usable with the atomic helpers, so let's start with the rename. Patch generated with coccinelle: @@ @@ -struct intel_crtc_config { +struct intel_crtc_state { ... } @@ @@ -struct intel_crtc_config +struct intel_crtc_state v2: Completely generate the patch with cocci. (Ander) Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NMatt Roper <matthew.d.roper@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
The performance regression from the CHV RC6 EI->TO change is now fixed so re-enable TO mode for better RC6 resicency. This reverts commit e85a5c79. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable the RP down timeout interrupt, and says that the timeout value is hence not used. We do enable that interrupt currently though, so leaving the timeout as 0 results in very poor performance as the GPU frequency keeps dropping constantly. So just program the register with the recommended value. Leaving the interrupt enabled doesn't seem to do any harm so far. So I've decided to leave it on for now, just to avoid making CHV a special case. This fixes the performance regression from: commit 5a0afd4b Author: Deepak S <deepak.s@linux.intel.com> Date: Sat Dec 13 11:43:27 2014 +0530 drm/i915/chv: Use timeout mode for RC6 on chv Cc: Deepak S <deepak.s@linux.intel.com> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
We use decimal for all the other RP magic values, so change GEN6_RP_DOWN_TIMEOUT to decimal as well. Also change the order of the register writes to match the BIOS spec for easier verification. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Deepak S<deepak.s@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Ville Syrjälä 提交于
Follow the sequence in the BIOS spec and clear the RC_CONTROL register before changing any of the other RC6/RP registers. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Deepak S<deepak.s@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Deepak S 提交于
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run. v2: reuse mask definitions & INTEL_INFO() to get device info (Ville) v3: add break in switch conditions (Ville) Signed-off-by: NDeepak S <deepak.s@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 13 1月, 2015 1 次提交
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由 Rodrigo Vivi 提交于
This reverts commit 5a0afd4b. Although timeout mode allows higher residency it impact badly on performance. I believe while we don't have a way to balance between performance and power savings at runtime I believe we have to revert and prioritize performance that was impacted a lot. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88103 Cc: Deepak S <deepak.s@linux.intel.com> Cc: Wendy Wang <wendy.wang@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 12 1月, 2015 3 次提交
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由 Imre Deak 提交于
We apply the RPS interrupt workaround on VLV everywhere except when writing the mask directly during idling the GPU. For consistency do this also there. While at it also extend the code comment about affected platforms. I couldn't reproduce the issue on VLV fixed by this workaround, by removing the workaround from everywhere, while it's 100% reproducible on SNB using igt/gem_reset_stats/ban-ctx-render. So also add a note that it hasn't been verified if the workaround really applies to VLV/CHV. Suggested-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NImre Deak <imre.deak@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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由 Imre Deak 提交于
In commit dbea3cea Author: Imre Deak <imre.deak@intel.com> Date: Mon Dec 15 18:59:28 2014 +0200 drm/i915: sanitize RPS resetting during GPU reset we disable RPS interrupts during GPU resetting, but don't apply the necessary GEN6 HW workaround. This leads to a HW lockup during a subsequent "looping batchbuffer" workload. This is triggered by the testcase that submits exactly this kind of workload after a simulated GPU reset. I'm not sure how likely the bug would have triggered otherwise, since we would have applied the workaround anyway shortly after the GPU reset, when enabling GT powersaving from the deferred work. This may also fix unrelated issues, since during driver loading / suspending we also disable RPS interrupts and so we also had a short window during the rest of the loading / resuming where a similar workload could run without the workaround applied. v2: - separate the fix to route RPS interrupts to the CPU on GEN9 too to a separate patch (Daniel) Bisected-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Testcase: igt/gem_reset_stats/ban-ctx-render Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87429Signed-off-by: NImre Deak <imre.deak@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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由 Imre Deak 提交于
GEN8+ HW has the option to route PM interrupts to either the CPU or to GT. For GEN8 this was already set correctly to routing to CPU, but not for GEN9, so fix this. Note that when disabling RPS interrupts this was set already correctly, though in that case it didn't matter much except for the possibility of spurious interrupts. Signed-off-by: NImre Deak <imre.deak@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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- 06 1月, 2015 1 次提交
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由 Kenneth Graunke 提交于
Haswell significantly improved the performance of sampler_c messages, but the optimization appears to be off by default. Later platforms remove this bit, and apparently always enable the optimization. Improves performance in "Counter Strike: Global Offensive" by 18% at default settings on Iris Pro. This may break sampling of paletted formats (P8/A8P8/P8A8). It's unclear whether it affects sampling of paletted formats in general, or just the sample_c message (which is never used). While libva does have support for using paletted formats (primarily for OSDs), that support appears to have been broken for at least a year, so I couldn't observe a regression from this: I tried to get libva-intel to use paletted formats, and observe a regression...but the only thing I found that used it was mplayer's OSD (on screen display). Even without my patch, the colors were totally wrong with that, and it's according to a few distro wikis, that's been the case for over a year. If libva's code for paletted formats /is/ broken, they could always add code to disable this bit using the command validator when fixing it. Further investigation from Haihao shows that libva mplayer OSD seems to work at least on his setup (still unclear what's wron with Ken's), and that it's not affected by this patch. Quoting the discussion between Haihao and Ken: > > > If you use "-vo gl" or "-vo xv", the OSD is solid white text with a black > > > border around it. I presume that it's supposed to be white with vaapi as > > > well, but I guess I'm not entirely sure. > > > > > > It's possible that the optimization doesn't affect the palette as long as > > > you never use sample_c with the paletted textures. > > > > I verified the palette takes effect in the following way: > > > > 1. Only support P8A8 format in the driver > > > > 2. ran the above command and I saw white OSD text > > > > 3. Only support P4A4 format in the driver and don't use > > 3DSTATE_SAMPLER_PALETTE_LOAD0 to load the value to the texture palette, > > so the palette keeps unchanged. > > > > 4. ran the above command and I saw black OSD text. > > > > 5. Load the right value to the texture palette and ran the above command > > again, I saw white OSD text. > > > > Hence I think sample_c with the paletted textures is used in the driver. > > That sounds like the palette is actually working, then. Great :) > > I doubt that libva would use sample_c - sampling with a shadow comparison? > It looks like it just uses sample and sample+killpix. You are right, libva driver doesn't use sample_c message. > I'm pretty sure the sample_c optimization just uses the palette memory as > storage for some stuff, so it's quite possible it just works if you're > only using sample and sample+killpix. Thanks for the explanation, it makes sense to me. Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> [danvet: Add wa name from Ville's review to the comment and copypaste the explanation why we don't care about libva (already broken) from Ken. Also add conclusion from libva devs that&why this is all fine.] Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Cc: "Xiang, Haihao" <haihao.xiang@intel.com> Cc: libva@lists.freedesktop.org Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 16 12月, 2014 2 次提交
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由 Deepak S 提交于
Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6. v2: Add comment about timeout threshold. (Tom) Signed-off-by: NDeepak S <deepak.s@linux.intel.com> Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Imre Deak 提交于
Atm, we don't disable RPS interrupts and related work items before resetting the GPU. This may interfere with the following GPU initialization and cause RPS interrupts to show up in PM_IIR too early before calling gen6_enable_rps_interrupts() (triggering a WARN there). Solve this by disabling RPS interrupts and flushing any related work items before resetting the GPU. v2: - split out the common parts of the gt suspend and the new gt reset functions (Paulo) v3: - remove the check for UMS, it's a NOP nowadays (Daniel) Reported-by: NHe, Shuang <shuang.he@intel.com> Testcase: igt/gem_reset_stats/ban-render Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86644Signed-off-by: NImre Deak <imre.deak@intel.com> Reviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com>
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- 15 12月, 2014 2 次提交
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由 Sonika Jindal 提交于
We were incorreectly bypassing the flush everytime which led to fifo underrun when more than one plane is enabled. Signed-off-by: NSonika Jindal <sonika.jindal@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Sonika Jindal 提交于
The pipe wm parameters is not correctly updated with sprite parameters because it copies them for each plane from plane_list to the sprite offset in pipe wm parameters. Since plane_list also contains primary and cursor planes, we end up updating wrong params for sprites. Signed-off-by: NSonika Jindal <sonika.jindal@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 11 12月, 2014 1 次提交
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由 Rodrigo Vivi 提交于
No functional changes. This is just the begin of a FBC rework. v2 (Paulo): - Revert intel_fbc_init() changed parameter. - Revert set_no_fbc_reason() rename. - Rebase. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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