On 32-bit machines, we can't divide 64-bit integers:

drivers/gpu/drm/arm/malidp_crtc.o: In function `malidp_crtc_atomic_check':
malidp_crtc.c:(.text.malidp_crtc_atomic_check+0x3c0): undefined reference to `__aeabi_uldivmod'
malidp_crtc.c:(.text.malidp_crtc_atomic_check+0x3dc): undefined reference to `__aeabi_uldivmod'

This calls the div_u64 function explicitly instead.

Fixes: 4cea4e9f6690 ("drm: mali-dp: Add plane upscaling support")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

When downscaling, mclk needs to be sufficiently higher than pxlclk in
order to be able to fetch the higher-resolution data and produce output
pixels. When not scaling, or when upscaling, mclk can be equal to
pxlclk. Since the driver doesn't control mclk, just ensure that the
requirement is satisfied with the current clock rate.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

Apply image enhacement when we are upscaling by a factor of 2
or more in either direction.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

Enable the scaling engine for upscaling a single plane using the polyphase
scaler. No image enhancement support or downscaling yet*, and composition
result scaling is not implemented.

* Downscaling a plane requires mclk > pxlclk.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

All DPs have a COLORADJ matrix which is applied prior to output gamma.
Attach that to the CTM property. Also, ensure the input CTM's coefficients
can fit in the DP registers' Q3.12 format.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

Add gamma via the DRM GAMMA_LUT/GAMMA_LUT_SIZE CRTC
properties. The expected LUT size is 4096 in order
to produce as accurate a set of segments as possible.

This version uses only the green channel's gamma curve
to set the hardware curve on DP550/650. For the sake of
simplicity, it uses the same table of coefficients for
all 3 curves on DP500.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <liviu.dudau@arm.com>

Add a custom CRTC state struct to enable storing driver's private
state. This patch only adds the base drm_crtc_state struct and
the atomic functions that handle it.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

Enable runtime and system Power Management. Clocks are now managed
from malidp_crtc_{enable,disable} functions. Suspend-to-RAM tested
as working on Juno.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

The rate of mclk depends on the use-case. If no downscaling is required,
then mclk == pxlclk is a valid option; with downscaling however, the
rate at which mclk runs determines how much a plane can be downscaled
before composition. This is a system integration + power management
issue that is more suited to firmware rather than this driver.
Signed-off-by: NMihail Atanassov <mihail.atanassov@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>

The vblank hooks in struct drm_driver are deprecated and only meant for
legacy drivers.  For modern drivers with DRIVER_MODESET flag, the hooks
in struct drm_crtc_funcs should be used instead.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1486458995-31018-6-git-send-email-shawnguo@kernel.org

Add support for the new family of Display Processors from ARM Ltd.
This commit adds basic support for Mali DP500, DP550 and DP650
parts, with only the display engine being supported at the moment.

Cc: David Brown <David.Brown@arm.com>
Cc: Brian Starkey <Brian.Starkey@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>