1. 02 9月, 2020 17 次提交
  2. 25 3月, 2020 1 次提交
  3. 18 3月, 2020 1 次提交
  4. 15 1月, 2020 1 次提交
    • F
      ICX: PCI: Add support for Immediate Readiness · aa7729ab
      Felipe Balbi 提交于
      commit d6112f8def514e019658bcc9b57d53acdb71ca3f upstream.
      
      PCIe r4.0, sec 7.5.1.1.4 defines a new bit in the Status Register:
      
        Immediate Readiness – This optional bit, when Set, indicates the Function
        is guaranteed to be ready to successfully complete valid configuration
        accesses at any time following any reset that the host is capable of
        issuing Configuration Requests to this Function.
      
        When this bit is Set, for accesses to this Function, software is exempt
        from all requirements to delay configuration accesses following any type
        of reset, including but not limited to the timing requirements defined in
        Section 6.6.
      
      This means that all delays after a Conventional or Function Reset can be
      skipped.
      
      This patch reads such bit and caches its value in a flag inside struct
      pci_dev to be checked later if we should delay or can skip delays after a
      reset.  While at that, also move the explicit msleep(100) call from
      pcie_flr() and pci_af_flr() to pci_dev_wait().
      Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>
      [bhelgaas: rename PCI_STATUS_IMMEDIATE to PCI_STATUS_IMM_READY]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NLin Wang <lin.x.wang@intel.com>
      Signed-off-by: NJeffle Xu <jefflexu@linux.alibaba.com>
      Acked-by: NJoseph Qi <joseph.qi@linux.alibaba.com>
      Acked-by: NCaspar Zhang <caspar@linux.alibaba.com>
      aa7729ab
  5. 27 12月, 2019 1 次提交
    • A
      PCI: Fix "try" semantics of bus and slot reset · e69730a1
      Alex Williamson 提交于
      commit ddefc033eecf23f1e8b81d0663c5db965adf5516 upstream
      
      The commit referenced below introduced device locking around save and
      restore of state for each device during a PCI bus "try" reset, making
      it decidely non-"try" and prone to deadlock in the event that a device
      is already locked.  Restore __pci_reset_bus() and __pci_reset_slot()
      to their advertised locking semantics by pushing the save and restore
      functions into the branch where the entire tree is already locked.
      Extend the helper function names with "_locked" and update the comment
      to reflect this calling requirement.
      
      Fixes: b014e96d ("PCI: Protect pci_error_handlers->reset_notify() usage with device_lock()")
      Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      Signed-off-by: NZhiyuan Hou <zhiyuan2048@linux.alibaba.com>
      Acked-by: NCaspar Zhang <caspar@linux.alibaba.com>
      e69730a1
  6. 21 12月, 2019 5 次提交
  7. 18 12月, 2019 2 次提交
    • Y
      PCI: rcar: Fix missing MACCTLR register setting in initialization sequence · 2de11b2e
      Yoshihiro Shimoda 提交于
      [ Upstream commit 7c7e53e1c93df14690bd12c1f84730fef927a6f1 ]
      
      The R-Car Gen2/3 manual - available at:
      
      https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg1m.html#documents
      
      "RZ/G Series User's Manual: Hardware" section
      
      strictly enforces the MACCTLR inizialization value - 39.3.1 - "Initial
      Setting of PCI Express":
      
      "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before
      enabling PCIETCTLR.CFINIT".
      
      To avoid unexpected behavior and to match the SW initialization sequence
      guidelines, this patch programs the MACCTLR with the correct value.
      
      Note that the MACCTLR.SPCHG bit in the MACCTLR register description
      reports that "Only writing 1 is valid and writing 0 is invalid" but this
      "invalid" has to be interpreted as a write-ignore aka "ignored", not
      "prohibited".
      Reported-by: NEugeniu Rosca <erosca@de.adit-jv.com>
      Fixes: c25da477 ("PCI: rcar: Add Renesas R-Car PCIe driver")
      Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
      Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
      Cc: <stable@vger.kernel.org> # v5.2+
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      2de11b2e
    • M
      ACPI / hotplug / PCI: Allocate resources directly under the non-hotplug bridge · 9f5ee706
      Mika Westerberg 提交于
      commit 77adf9355304f8dcf09054280af5e23fc451ab3d upstream.
      
      Valerio and others reported that commit 84c8b58e ("ACPI / hotplug /
      PCI: Don't scan bridges managed by native hotplug") prevents some recent
      LG and HP laptops from booting with endless loop of:
      
        ACPI Error: No handler or method for GPE 08, disabling event (20190215/evgpe-835)
        ACPI Error: No handler or method for GPE 09, disabling event (20190215/evgpe-835)
        ACPI Error: No handler or method for GPE 0A, disabling event (20190215/evgpe-835)
        ...
      
      What seems to happen is that during boot, after the initial PCI enumeration
      when EC is enabled the platform triggers ACPI Notify() to one of the root
      ports. The root port itself looks like this:
      
        pci 0000:00:1b.0: PCI bridge to [bus 02-3a]
        pci 0000:00:1b.0:   bridge window [mem 0xc4000000-0xda0fffff]
        pci 0000:00:1b.0:   bridge window [mem 0x80000000-0xa1ffffff 64bit pref]
      
      The BIOS has configured the root port so that it does not have I/O bridge
      window.
      
      Now when the ACPI Notify() is triggered ACPI hotplug handler calls
      acpiphp_native_scan_bridge() for each non-hotplug bridge (as this system is
      using native PCIe hotplug) and pci_assign_unassigned_bridge_resources() to
      allocate resources.
      
      The device connected to the root port is a PCIe switch (Thunderbolt
      controller) with two hotplug downstream ports. Because of the hotplug ports
      __pci_bus_size_bridges() tries to add "additional I/O" of 256 bytes to each
      (DEFAULT_HOTPLUG_IO_SIZE). This gets further aligned to 4k as that's the
      minimum I/O window size so each hotplug port gets 4k I/O window and the
      same happens for the root port (which is also hotplug port). This means
      3 * 4k = 12k I/O window.
      
      Because of this pci_assign_unassigned_bridge_resources() ends up opening a
      I/O bridge window for the root port at first available I/O address which
      seems to be in range 0x1000 - 0x3fff. Normally this range is used for ACPI
      stuff such as GPE bits (below is part of /proc/ioports):
      
          1800-1803 : ACPI PM1a_EVT_BLK
          1804-1805 : ACPI PM1a_CNT_BLK
          1808-180b : ACPI PM_TMR
          1810-1815 : ACPI CPU throttle
          1850-1850 : ACPI PM2_CNT_BLK
          1854-1857 : pnp 00:05
          1860-187f : ACPI GPE0_BLK
      
      However, when the ACPI Notify() happened this range was not yet reserved
      for ACPI/PNP (that happens later) so PCI gets it. It then starts writing to
      this range and accidentally stomps over GPE bits among other things causing
      the endless stream of messages about missing GPE handler.
      
      This problem does not happen if "pci=hpiosize=0" is passed in the kernel
      command line. The reason is that then the kernel does not try to allocate
      the additional 256 bytes for each hotplug port.
      
      Fix this by allocating resources directly below the non-hotplug bridges
      where a new device may appear as a result of ACPI Notify(). This avoids the
      hotplug bridges and prevents opening the additional I/O window.
      
      Fixes: 84c8b58e ("ACPI / hotplug / PCI: Don't scan bridges managed by native hotplug")
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=203617
      Link: https://lore.kernel.org/r/20191030150545.19885-1-mika.westerberg@linux.intel.comReported-by: NValerio Passini <passini.valerio@gmail.com>
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      9f5ee706
  8. 05 12月, 2019 1 次提交
    • M
      PCI/MSI: Return -ENOSPC from pci_alloc_irq_vectors_affinity() · 3e059545
      Ming Lei 提交于
      [ Upstream commit 77f88abd4a6f73a1a68dbdc0e3f21575fd508fc3 ]
      
      The API of pci_alloc_irq_vectors_affinity() says it returns -ENOSPC if
      fewer than @min_vecs interrupt vectors are available for @dev.
      
      However, if a device supports MSI-X but not MSI and a caller requests
      @min_vecs that can't be satisfied by MSI-X, we previously returned -EINVAL
      (from the failed attempt to enable MSI), not -ENOSPC.
      
      When -ENOSPC is returned, callers may reduce the number IRQs they request
      and try again.  Most callers can use the @min_vecs and @max_vecs
      parameters to avoid this retry loop, but that doesn't work when using IRQ
      affinity "nr_sets" because rebalancing the sets is driver-specific.
      
      This return value bug has been present since pci_alloc_irq_vectors() was
      added in v4.10 by aff17164 ("PCI: Provide sensible IRQ vector
      alloc/free routines"), but it wasn't an issue because @min_vecs/@max_vecs
      removed the need for callers to iteratively reduce the number of IRQs
      requested and retry the allocation, so they didn't need to distinguish
      -ENOSPC from -EINVAL.
      
      In v5.0, 6da4b3ab9a6e ("genirq/affinity: Add support for allocating
      interrupt sets") added IRQ sets to the interface, which reintroduced the
      need to check for -ENOSPC and possibly reduce the number of IRQs requested
      and retry the allocation.
      Signed-off-by: NMing Lei <ming.lei@redhat.com>
      [bhelgaas: changelog]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Jens Axboe <axboe@fb.com>
      Cc: Keith Busch <keith.busch@intel.com>
      Cc: Christoph Hellwig <hch@lst.de>
      Signed-off-by: NSasha Levin <sashal@kernel.org>
      3e059545
  9. 01 12月, 2019 5 次提交
  10. 21 11月, 2019 6 次提交