- 08 11月, 2017 4 次提交
-
-
由 Markus Elfring 提交于
* Add a jump target so that a specific error message is stored only once at the end of this function implementation. * Replace two calls of the function "dev_err" by goto statements. * Adjust two condition checks. This issue was detected by using the Coccinelle software. Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: NHans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
We can just use the generic Device Tree parser code in this driver and save some code. Acked-by: NHans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Acked-by: NRob Herring <robh@kernel.org> Acked-by: NHans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
- 31 10月, 2017 8 次提交
-
-
由 Ken Ma 提交于
Current edge both type gpio irqs which need to swap polarity in each interrupt are not supported, this patch adds edge both type gpio irq support. Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Masahiro Yamada 提交于
This is handled by the mmc-pwrseq-emmc driver, which controls an eMMC hardware reset via a GPIO line. Remove it from the function pin-mux settings. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Heiko Stuebner 提交于
The rk3288 also has one function that can be routed to one of two pins, the hdmi cec functionality can use either gpio7c0 or gpio7c7. So add the route switching support for it. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NHans Verkuil <hans.verkuil@cisco.com> Reviewed-by: NDavid Wu <david.wu@rock-chips.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Mika Westerberg 提交于
Intel Cedar Fork PCH is the successor of Intel Denverton PCH but it is based on the newer GPIO/pinctrl hardware block. Add a new pinctrl/GPIO driver to support it. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Mika Westerberg 提交于
Some GPIO blocks have the interrupt status (GPI_IS) offset different than it normally is, so make it configurable. If no offset is specified we use the default. While there remove two unused constants from the core driver. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Maxime Ripard 提交于
The strict mode should always have been enabled on our driver, and leaving it unchecked just makes it harder to find a migration path as time passes. Let's enable it by default now so that hopefully the new SoCs should be safe. Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Maxime Ripard 提交于
Old pinctrl drivers will need to disable strict mode for various reasons, among which: - Some DT will still have a pinctrl group for each GPIO used, which will be rejected by pin_request. While we could remove those nodes, we still have to deal with old DTs. - Some GPIOs on these boards need to have their pin configuration changed (for bias or current), and there's no clear migration path Let's disable the strict mode on those SoCs so that there's no breakage. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Maxime Ripard 提交于
Our pinctrl device should have had strict set all along. However, it wasn't the case, and most of our old device trees also have a pinctrl group in addition to the GPIOs properties, which mean that we can't really turn it on now. All our new SoCs don't have that group, so we should still enable that mode on the newer one though. In order to enable it by default, add a flag that will allow to disable that mode that should be set by pinctrl drivers that cannot be migrated. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
- 20 10月, 2017 15 次提交
-
-
由 Linus Walleij 提交于
Merge tag 'sh-pfc-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 (take two) - Add Audio, HSCIF, I2C, and INTC-EX pin groups on R-Car H3 ES2.0, - Add Audio and PWM pin groups on R-Car D3, - Add support for RZ/A1M and RZ/A1L, - Add INTC-EX pin groups on R-Car M3-W, - Add SDHI voltage switching on RZ/G1E, - Make bias control and IOCTRL support more generic, - Add suspend/resume support for R-Car Gen3, - Small fixes and cleanups.
-
由 Geert Uytterhoeven 提交于
During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their pinctrl register state is lost. Note that as the boot loader skips most initialization after system resume, pinctrl register state differs from the state encountered during normal system boot, too. To fix this, save all GPIO and peripheral function select, module select, drive strength control, bias, and other I/O control registers during system suspend, and restore them during system resume. Note that to avoid overhead on platforms not needing it, the suspend/resume code has a build time dependency on sleep and PSCI support, and a runtime dependency on PSCI. Inspired by a patch in the BSP by Hien Dang. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car M3-W I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car H3 ES2.0 I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car H3 ES1.x I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage and time delay control), like is already done for config, drive, and bias registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
All users of sh_pfc_pin_to_bias_info() and the related data structures have been converted to sh_pfc_pin_to_bias_reg(), so those can be removed. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
由 Geert Uytterhoeven 提交于
Move R-Car M1A bias support over to the generic way to describe bias registers. As the new description is more compact, this decreases kernel size by ca. 148 bytes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car M3-W bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car H3 ES2.0 bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 308 bytes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car H3 ES1.x bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
由 Geert Uytterhoeven 提交于
Add a helper to look up bias registers and bit number for a specific pin, using the generic bias register description. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Add a generic way to describe bias registers (for pull-up/down control), like is already done for config and drive registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
由 Geert Uytterhoeven 提交于
On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
由 Geert Uytterhoeven 提交于
As of commit 8682b3c5 ("sh-pfc: Remove platform device registration"), plain "sh-pfc" platform devices are no longer created. Hence remove their match entry, and the now obsolete checks for missing device IDs and driver data. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
- 19 10月, 2017 3 次提交
-
-
由 Phil Reid 提交于
This adds the required definitions for the mcp23018 which is the i2c variant of the mcp23s18. Signed-off-by: NPhil Reid <preid@electromag.com.au> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
When making the pin control submenu globally visible, all kinds of oddities appear, in blackfin a few files were #including <linux/gpio.h> and relying on that to pull in <asm/gpio.h>. This was not working when pin control but not GPIOLIB was selected resulting in a breakage in allmodconfig. The code these files were using was still there and defined in <asm/gpio.h> just not pulle in from just including <linux/gpio.h> Simply add the required includes explicitly in the blackfin kernel core and everything compiles fine. Delete the use of the incorrect <linux/gpio.h> where possible. Add stubs to <asm/gpio.h> for the functions called from PM: these should probably also depend on !PINCTRL but since the global CONFIG_PM symbol is used to compile PM support, we need some more intrusive thing here, to be tested by Blackfin maintainers. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
The build robot is complaining on Blackfin: drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup': >> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing pointer to incomplete type 'struct gpio_port_t' writew(readw(®s->port_fer) & ~BIT(offset), ^~ drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq': >> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing pointer to incomplete type 'struct bfin_pint_regs' if (readl(®s->invert_set) & pintbit) ^~ It seems the driver need to include <asm/gpio.h> and <asm/irq.h> to compile. The Blackfin architecture was re-defining the Kconfig PINCTRL symbol which is not OK, so replaced this with PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2 just like most arches do. Further, the old GPIO driver symbol GPIO_ADI was possible to select at the same time as selecting PINCTRL. This was not working because the arch-local <asm/gpio.h> header contains an explicit #ifndef PINCTRL clause making compilation break if you combine them. The same is true for DEBUG_MMRS. Make sure the ADI2 pinctrl driver is not selected at the same time as the old GPIO implementation. (This should be converted to use gpiolib or pincontrol and move to drivers/...) Also make sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at the same time as the new PINCTRL implementation, and only make PINCTRL_ADI2 selectable for the Blackfin families that actually have it. This way it is still possible to add e.g. I2C-based pin control expanders on the Blackfin. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
- 17 10月, 2017 4 次提交
-
-
由 Linus Walleij 提交于
The SX150X driver was moved over to pin control a while back. The GPIO Kconfig symbol creates a circular dependency since it requires GPIOLIB and the pin control driver selects GPIOLIB so get rid of the old annoying Kconfig option. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Jerome Brunet 提交于
This change prepare the introduction of new meson SoC. This new SoC will share the same gpio/pinconf registers but the pinmux part will be different. While the format of the data associated with each pinmux group will change, the way to handle pinmuxing will be similar. To deal with this new situation, the meson_pmx_struture is kept but the data associated to it is now generic. This allows to reuse the basic functions which would otherwise be copy/pasted in each pinmux driver (such as getting the name a count of groups and functions) Only the functions actually using this specific data is taken out of the common code and is handling the SoC pinmuxing Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Jerome Brunet 提交于
When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Miquel Raynal 提交于
Fix a typo in A37xx pin controllers documentation about uart2 pin group. Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
- 16 10月, 2017 2 次提交
-
-
由 Biju Das 提交于
Voltage switching is the same as on the r8a7794. Signed-off-by: NBiju Das <biju.das@bp.renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017 removed the USB0_IDIN and USB0_IDPU pins on R-Car D3. This change has no functional impact, as these definitions were unused. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 15 10月, 2017 1 次提交
-
-
由 Linus Walleij 提交于
Some two functions were missing from the Gemini pin control driver. Noticed when trying to use ethernet. Fix it up by adding them. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
- 12 10月, 2017 1 次提交
-
-
由 Linus Walleij 提交于
Instead of depends on GPIOLIB and having to run around in Kconfig menus looking for why your device is not available, simply select it from the pin control drivers that need it. The Kconfig for GPIOLIB is improved, selectable and this should "just work". Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
- 11 10月, 2017 2 次提交
-
-
由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-