- 09 11月, 2017 1 次提交
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由 Masahiro Yamada 提交于
We need to add "clean-files" in Makfiles to clean up DT blobs, but we often miss to do so. Since there are no source files that end with .dtb or .dtb.S, so we can clean-up those files from the top-level Makefile. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NRob Herring <robh@kernel.org>
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- 24 8月, 2017 1 次提交
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由 Hanna Hawa 提交于
This commit adds the base Device Tree files for the Armada 8KPlus. The Armada 8KP SoCs include several hardware blocks, and this commit only adds support for the AP810 block, that contains the CPU core and basic peripherals. AP810 is a high-performance die, includes octal core application processor based ARMv8-A architecture, two standard high speed DDR4 interface, and GIC-600 interrupt controller. AP810 Built as part of Marvell’s MoChi AP family products. Armada-8080 (8KPlus family), include an AP810 block that contains the CPU core and basic peripherals. This commit creates the following hierarchy: * armada-ap810-ap0.dtsi - definitions common to AP810 * armada-ap810-ap0-octa-core.dtsi - description of the octa cores * armada-8080.dtsi - description of the 8080 SoC * armada-8080-db.dts - description of the 8080 board Signed-off-by: NHanna Hawa <hannah@marvell.com> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 20 1月, 2017 1 次提交
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由 Russell King 提交于
Add a cut-down version of the DTS file for the community board MACCHIATOBin from SolidRun based on Marvell Armada 8040 SoC to suit the current mainlined Armada 8040 state. This brings support for mainly SATA, SPI flash and UART. The USB descriptions are included but are not tested in this form due to the lack of mainline GPIO. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Acked-by: NRabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 17 10月, 2016 1 次提交
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由 Romain Perier 提交于
This is a high performance 64 bit dual core low power consuming networking computing platform based on the ARMv8 architecture. It contains an Armada 3720 running up to 1.2Ghz. This commit adds a basic definition for this board. Signed-off-by: NRomain Perier <romain.perier@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 08 8月, 2016 1 次提交
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由 Thomas Petazzoni 提交于
This commit adds a Device Tree description for the Marvell Armada 8040 Development Board. It features a quad-core Cortex A72 Armada 8040 SoC, with a large number of peripherals: dual Gigabit, dual 10 GBit, 6 PCIe interfaces, 6 SATA ports, 4 USB 3.0 ports, and more. Only a subset of the functionalities are supported so far, and additional features will be progressively enabled in the future. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 26 2月, 2016 1 次提交
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由 Thomas Petazzoni 提交于
This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board. The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of: - An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040). - One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces. In order to represent this from a Device Tree point of view, this commit creates the following hierarchy: * armada-ap806.dtsi - definitions common to dual/quad ap806 * armada-ap806-dual.dtsi - description of the two CPUs * armada-7020.dtsi - description of the 7020 SoC * armada-8020.dtsi - description of the 8020 SoC * armada-ap806-quad.dtsi - description of the four CPUs * armada-7040.dtsi - description of the 7040 SoC * armada-7040-db.dts - description of the 7040 board * armada-8040.dtsi - description of the 8040 SoC The CP110 blocks are not described yet, and will be part of future patch series. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 17 2月, 2016 1 次提交
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由 Gregory CLEMENT 提交于
Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53 CPUs. There are two members in this family: the Armada 3710 (Single CPU) and the Armada 3720 (Dual CPUs). It also adds a dts file for the Marvell Armada 3720 DB board. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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- 21 9月, 2015 1 次提交
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由 Jisheng Zhang 提交于
This patch adds dts for the Berlin4CT STB reference board which is also based on the Berlin4CT SoC. The Berlin4CT DMP board will be deprecated as time goes. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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- 04 8月, 2015 1 次提交
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由 Jisheng Zhang 提交于
Add initial dtsi file to support Marvell Berlin4CT SoC with quad Cortex-A53 CPUs. It also adds dts file for Marvell Berlin4CT DMP board which is based on Berlin4CT SoC. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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- 24 7月, 2015 1 次提交
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由 Mars Cheng 提交于
This adds basic chip support for MT6795 SoC Signed-off-by: NMars Cheng <mars.cheng@mediatek.com> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 26 1月, 2015 1 次提交
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由 Eddie Huang 提交于
Add device tree support for MT8173 SoC and evaluation board based on it. Signed-off-by: NEddie Huang <eddie.huang@mediatek.com> Acked-by: Arnd Bergmann <arnd at arndb.de> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 22 10月, 2014 1 次提交
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由 Robert Richter 提交于
Moving dts files to vendor subdirs. Acked-by: NRob Herring <robh@kernel.org> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRobert Richter <rrichter@cavium.com>
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