We need to add "clean-files" in Makfiles to clean up DT blobs, but we
often miss to do so.

Since there are no source files that end with .dtb or .dtb.S, so we
can clean-up those files from the top-level Makefile.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NRob Herring <robh@kernel.org>

The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: NDuc Dang <dhdang@apm.com>
Acked-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Add a non-zero ranges property for /soc node
v3: change #address-cells and #size-cells to <2>
    change the GIC address to 0xfffc1000
    update the GIC virtual CPU reg length to 0x2000
v2: use interrupt-affinity for pmu node