1. 10 3月, 2010 26 次提交
    • P
      perf, x86: Clear the LBRs on init · 74846d35
      Peter Zijlstra 提交于
      Some CPUs have errata where the LBR is not cleared on Power-On. So always
      clear the LBRs before use.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100305154128.966563424@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      74846d35
    • P
      perf, x86: Disable PEBS on clovertown chips · 3c44780b
      Peter Zijlstra 提交于
      This CPU has just too many handycaps to be really useful.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100305154128.890278662@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3c44780b
    • P
      perf, x86: Fix silly bug in data store buffer allocation · 3adaebd6
      Peter Zijlstra 提交于
      Fix up the ds allocation error path, where we could free @buffer before
      we used it.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100305154128.813452402@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3adaebd6
    • P
      x86: Move MAX_INSN_SIZE into asm/insn.h · 30a813ae
      Peter Zijlstra 提交于
      Since there's now two users for this, place it in a common header.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: Masami Hiramatsu <mhiramat@redhat.com>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.923774125@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      30a813ae
    • P
      perf, x86: Expose the full PEBS record using PERF_SAMPLE_RAW · 7e1a40dd
      Peter Zijlstra 提交于
      Expose the full PEBS record using PERF_SAMPLE_RAW
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.847218224@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7e1a40dd
    • P
      perf, x86: Clean up IA32_PERF_CAPABILITIES usage · 8db909a7
      Peter Zijlstra 提交于
      Saner PERF_CAPABILITIES support, which also exposes pebs_trap. Use that
      latter to make PEBS's use of LBR conditional since a fault-like pebs
      should already report the correct IP.
      
      ( As of this writing there is no known hardware that implements
        !pebs_trap )
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.770650663@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8db909a7
    • P
      perf-top: Show the percentage of successfull PEBS-fixups · 1676b8a0
      Peter Zijlstra 提交于
      Use the PERF_RECORD_MISC_EXACT information to measure the success rate of
      the PEBS fix-up.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.694233760@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1676b8a0
    • P
      perf, x86: use LBR for PEBS IP+1 fixup · ef21f683
      Peter Zijlstra 提交于
      Use the LBR to fix up the PEBS IP+1 issue.
      
      As said, PEBS reports the next instruction, here we use the LBR to find
      the last branch and from that construct the actual IP. If the IP matches
      the LBR-TO, we use LBR-FROM, otherwise we use the LBR-TO address as the
      beginning of the last basic block and decode forward.
      
      Once we find a match to the current IP, we use the previous location.
      
      This patch introduces a new ABI element: PERF_RECORD_MISC_EXACT, which
      conveys that the reported IP (PERF_SAMPLE_IP) is the exact instruction
      that caused the event (barring CPU errata).
      
      The fixup can fail due to various reasons:
      
       1) LBR contains invalid data (quite possible)
       2) part of the basic block got paged out
       3) the reported IP isn't part of the basic block (see 1)
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: Masami Hiramatsu <mhiramat@redhat.com>
      Cc: "Zhang, Yanmin" <yanmin_zhang@linux.intel.com>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.619375431@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ef21f683
    • P
      perf, x86: Implement simple LBR support · caff2bef
      Peter Zijlstra 提交于
      Implement simple suport Intel Last-Branch-Record, it supports all
      hardware that implements FREEZE_LBRS_ON_PMI, but does not (yet) implement
      the LBR config register.
      
      The Intel LBR is a FIFO of From,To addresses describing the last few
      branches the hardware took.
      
      This patch does not add perf interface to the LBR, but merely provides an
      interface for internal use.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.544191154@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      caff2bef
    • P
      perf: Add attr->precise support to raw event parsing · 69fef0d2
      Peter Zijlstra 提交于
      Minimal userspace interface to the new 'precise' events flag.
      
      Can be used like "perf top -e r00c0p" which will use PEBS to sample
      retired instructions.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.468665803@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      69fef0d2
    • P
      perf, x86: Add PEBS infrastructure · ca037701
      Peter Zijlstra 提交于
      This patch implements support for Intel Precise Event Based Sampling,
      which is an alternative counter mode in which the counter triggers a
      hardware assist to collect information on events. The hardware assist
      takes a trap like snapshot of a subset of the machine registers.
      
      This data is written to the Intel Debug-Store, which can be programmed
      with a data threshold at which to raise a PMI.
      
      With the PEBS hardware assist being trap like, the reported IP is always
      one instruction after the actual instruction that triggered the event.
      
      This implements a simple PEBS model that always takes a single PEBS event
      at a time. This is done so that the interaction with the rest of the
      system is as expected (freq adjust, period randomization, lbr,
      callchains, etc.).
      
      It adds an ABI element: perf_event_attr::precise, which indicates that we
      wish to use this (constrained, but precise) mode.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <20100304140100.392111285@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ca037701
    • P
      perf: Provide better condition for event rotation · d4944a06
      Peter Zijlstra 提交于
      Try to avoid useless rotation and PMU disables.
      
      [ Could be improved by keeping a nr_runnable count to better account
        for the < PERF_STAT_INACTIVE counters ]
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d4944a06
    • P
      perf, x86: Fix double enable calls · f3d46b2e
      Peter Zijlstra 提交于
      hw_perf_enable() would enable already enabled events.
      
      This causes problems with code that assumes that ->enable/->disable calls
      are balanced (like the LBR code does).
      
      What happens is that events that were already running and left in place
      would get enabled again.
      
      Avoid this by only enabling new events that match their previous
      assignment.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f3d46b2e
    • P
      perf, x86: Fix double disable calls · 19925ce7
      Peter Zijlstra 提交于
      hw_perf_enable() would disable events that were not yet enabled.
      
      This causes problems with code that assumes that ->enable/->disable calls
      are balanced (like the LBR code does).
      
      What happens is that we disable newly added counters that match their
      previous assignment, even though they are not yet programmed on the
      hardware.
      
      Avoid this by only doing the first pass over the existing events.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      19925ce7
    • P
      perf, x86: Properly account n_added · 356e1f2e
      Peter Zijlstra 提交于
      Make sure n_added is properly accounted so that we can rely on the value
      to reflect the number of added counters. This is needed if its going to
      be used for more than a boolean check.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      356e1f2e
    • P
      perf, x86: Avoid double disable on throttle vs ioctl(PERF_IOC_DISABLE) · 71e2d282
      Peter Zijlstra 提交于
      Calling ioctl(PERF_EVENT_IOC_DISABLE) on a thottled counter would result
      in a double disable, cure this by using x86_pmu_{start,stop} for
      throttle/unthrottle and teach x86_pmu_stop() to check ->active_mask.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      71e2d282
    • P
      perf, x86: Fix x86_pmu_start · c08053e6
      Peter Zijlstra 提交于
      pmu::start should undo pmu::stop, make it so.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c08053e6
    • P
      perf, x86: Use unlocked bitops · 34538ee7
      Peter Zijlstra 提交于
      There is no concurrency on these variables, so don't use LOCK'ed ops.
      
      As to the intel_pmu_handle_irq() status bit clean, nobody uses that so
      remove it all together.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      LKML-Reference: <20100304140100.240023029@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      34538ee7
    • P
      perf, x86: Change x86_pmu.{enable,disable} calling convention · aff3d91a
      Peter Zijlstra 提交于
      Pass the full perf_event into the x86_pmu functions so that those may
      make use of more than the hw_perf_event, and while doing this, remove the
      superfluous second argument.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      LKML-Reference: <20100304140100.165166129@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      aff3d91a
    • P
      perf, x86: Remove superfluous arguments to x86_perf_event_update() · cc2ad4ba
      Peter Zijlstra 提交于
      The second and third argument to x86_perf_event_update() are superfluous
      since they are simple expressions of the first argument. Hence remove
      them.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      LKML-Reference: <20100304140100.089468871@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cc2ad4ba
    • P
      perf, x86: Remove superfluous arguments to x86_perf_event_set_period() · 07088edb
      Peter Zijlstra 提交于
      The second and third argument to x86_perf_event_set_period() are
      superfluous since they are simple expressions of the first argument.
      Hence remove them.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      LKML-Reference: <20100304140100.006500906@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      07088edb
    • P
      perf, x86, Do not user perf_disable from NMI context · 3fb2b8dd
      Peter Zijlstra 提交于
      Explicitly use intel_pmu_{disable,enable}_all() in intel_pmu_handle_irq()
      to avoid the NMI race conditions in perf_{disable,enable}
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3fb2b8dd
    • P
      perf: Optimize perf_disable · 32975a4f
      Peter Zijlstra 提交于
      Currently we always call hw_perf_disable(), even if its already disabled,
      this seems superflous, esp. since it cannot be made NMI safe (see further
      patches).
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      LKML-Reference: <new-submission>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      32975a4f
    • P
      perf: Rework and fix the arch CPU-hotplug hooks · 3f6da390
      Peter Zijlstra 提交于
      Remove the hw_perf_event_*() hotplug hooks in favour of per PMU hotplug
      notifiers. This has the advantage of reducing the static weak interface
      as well as exposing all hotplug actions to the PMU.
      
      Use this to fix x86 hotplug usage where we did things in ONLINE which
      should have been done in UP_PREPARE or STARTING.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: paulus@samba.org
      Cc: eranian@google.com
      Cc: robert.richter@amd.com
      Cc: fweisbec@gmail.com
      Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
      LKML-Reference: <20100305154128.736225361@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3f6da390
    • P
      perf: Provide generic perf_sample_data initialization · dc1d628a
      Peter Zijlstra 提交于
      This makes it easier to extend perf_sample_data and fixes a bug on arm
      and sparc, which failed to set ->raw to NULL, which can cause crashes
      when combined with PERF_SAMPLE_RAW.
      
      It also optimizes PowerPC and tracepoint, because the struct
      initialization is forced to zero out the whole structure.
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Acked-by: NJean Pihet <jpihet@mvista.com>
      Reviewed-by: NFrederic Weisbecker <fweisbec@gmail.com>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      Cc: Jamie Iles <jamie.iles@picochip.com>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: stable@kernel.org
      LKML-Reference: <20100304140100.315416040@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      dc1d628a
    • I
      Merge commit 'v2.6.34-rc1' into perf/urgent · 548b8416
      Ingo Molnar 提交于
      Conflicts:
      	tools/perf/util/probe-event.c
      
      Merge reason: Pick up -rc1 and resolve the conflict as well.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      548b8416
  2. 09 3月, 2010 3 次提交
  3. 08 3月, 2010 11 次提交