1. 05 8月, 2010 17 次提交
  2. 27 7月, 2010 2 次提交
  3. 06 7月, 2010 4 次提交
  4. 28 5月, 2010 1 次提交
  5. 22 5月, 2010 6 次提交
  6. 21 5月, 2010 1 次提交
    • J
      mips,kgdb: kdb low level trap catch and stack trace · 5dd11d5d
      Jason Wessel 提交于
      The only way the debugger can handle a trap in inside rcu_lock,
      notify_die, or atomic_notifier_call_chain without a recursive fault is
      to have a low level "first opportunity handler" do_trap_or_bp() handler.
      
      Generally this will be something the vast majority of folks will not
      need, but for those who need it, it is added as a kernel .config
      option called KGDB_LOW_LEVEL_TRAP.
      
      Also added was a die notification for oops such that kdb can catch an
      oops for analysis.
      
      There appeared to be no obvious way to pass the struct pt_regs from
      the original exception back to the stack back tracer, so a special
      case was added to show_stack() for when kdb is active because you
      generally desire to generally look at the back trace of the original
      exception.
      Signed-off-by: NJason Wessel <jason.wessel@windriver.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      5dd11d5d
  7. 17 5月, 2010 1 次提交
  8. 16 5月, 2010 1 次提交
    • S
      MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 · 95e8f634
      Shane McDonald 提交于
          
          In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
          are not currently writeable by the ctc1 instruction.  In odd corner cases,
          this can cause problems.  For example, a case existed where a divide-by-zero
          exception was generated by the FPU, and the signal handler attempted to
          restore the FPU registers to their state before the exception occurred.  In
          this particular setup, writing the old value to the FCSR register would
          cause another divide-by-zero exception to occur immediately.  The solution
          is to change the ctc1 instruction emulator code to allow the Cause bits of
          the FCSR register to be writeable.  This is the behaviour of the hardware
          that the code is emulating.
          
          This problem was found by Shane McDonald, but the credit for the fix goes
          to Kevin Kissell.  In Kevin's words:
          
          I submit that the bug is indeed in that ctc_op:  case of the emulator.  The
          Cause bits (17:12) are supposed to be writable by that instruction, but the
          CTC1 emulation won't let them be updated by the instruction.  I think that
          actually if you just completely removed lines 387-388 [...] things would
          work a good deal better.  At least, it would be a more accurate emulation of
          the architecturally defined FPU.  If I wanted to be really, really pedantic
          (which I sometimes do), I'd also protect the reserved bits that aren't
          necessarily writable.
      Signed-off-by: NShane McDonald <mcdonald.shane@gmail.com>
          To: anemo@mba.ocn.ne.jp
          To: kevink@paralogos.com
          To: sshtylyov@mvista.com
          Patchwork: http://patchwork.linux-mips.org/patch/1205/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      
      ---
      95e8f634
  9. 14 5月, 2010 1 次提交
  10. 01 5月, 2010 6 次提交