- 07 5月, 2015 1 次提交
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由 Peter Griffin 提交于
Ths picophyreset is incorrectly defined, which stops the usb2 phy being taken out of reset. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Acked-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 30 4月, 2015 3 次提交
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由 Peter Griffin 提交于
Now that the miphy28lp is upstream, we can add the sata dt nodes for stih407 family silicon. This has been tested on b2120 board J4 (sata0 channel). These nodes are disabled by default as a special mini pci-e to sata daughter board is required which isn't shipped with the board. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Acked-by: NLee Jones <lee.jones@linaro.org> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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由 Lee Jones 提交于
On current ST platforms the LPC controls a number of functions. This patch enables support for the LPC Watchdog and LPC RTC devices on LPC1 and LPC2 respectively. Signed-off-by: NDavid Paris <david.paris@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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由 Peter Griffin 提交于
The nodes have been split to allow as much commonality as possible. The stih407 has a silicon bug with eMMC UHS modes (with top regs) and as such doesn't have any of the uhs dt properties. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 29 4月, 2015 2 次提交
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由 Lee Jones 提交于
The Synchronous Serial Controller is used to provide SPI. These are the ports which are located on the Stand-By Controller (SBC). Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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由 Lee Jones 提交于
The Synchronous Serial Controller is used to provide SPI. Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 16 1月, 2015 1 次提交
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由 Gabriel FERNANDEZ 提交于
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or USB3 devices. The two first ports can be use for either; both SATA, both PCIe or one of each in any configuration. The Third port is only for USB3. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 12 1月, 2015 1 次提交
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由 Peter Griffin 提交于
This patch adds the dt nodes for the usb2 picophy found on the stih407 device family. It is used on stih407 by the dwc3 usb3 controller when controlling usb2/1.1 devices. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 09 1月, 2015 1 次提交
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由 Peter Griffin 提交于
This patch adds the dt nodes for the usb2 picophy found on the stih407 device family. It is used on stih407 by the dwc3 usb3 controller when controlling usb2/1.1 devices. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 18 11月, 2014 1 次提交
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由 Peter Griffin 提交于
The stih410 soc which will be added in the following commit is very similar to the stih407, to enable maximum re-use of the dt files this commit abstracts the common parts into a shared dt file stihxxx-b2120 for the board, and also a shared file stih407-family.dtsi for the SoC. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 31 10月, 2014 2 次提交
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由 Gabriel FERNANDEZ 提交于
Patch adds DT entries for clockgen C0 Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NOlivier Bideau <olivier.bideau@st.com> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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由 Peter Griffin 提交于
This patch adds the reset controller DT nodes for the powerdown, softreset and picophy controllers. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 21 5月, 2014 1 次提交
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由 Maxime Coquelin 提交于
The STiH407 is advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU. Acked-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: NLee Jones <lee.jones@linaro.org> Acked-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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