1. 26 2月, 2009 1 次提交
    • P
      perfcounters/powerpc: Add support for POWER5 processors · 742bd95b
      Paul Mackerras 提交于
      This adds the back-end for the PMU on the POWER5 processor.  This knows
      how to use the fixed-function PMC5 and PMC6 (instructions completed and
      run cycles).  Unlike POWER6, PMC5/6 obey the freeze conditions and can
      generate interrupts, so their use doesn't impose any extra restrictions.
      
      POWER5+ is different and is not supported by this patch.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      742bd95b
  2. 23 2月, 2009 1 次提交
    • P
      perfcounters/powerpc: Make exclude_kernel bit work on Apple G5 processors · d095cd46
      Paul Mackerras 提交于
      Currently, setting hw_event.exclude_kernel does nothing on the PPC970
      variants used in Apple G5 machines, because they have the HV (hypervisor)
      bit in the MSR forced to 1, so as far as the PMU is concerned, the
      kernel runs in hypervisor mode.  Thus we have to use the MMCR0_FCHV
      (freeze counters in hypervisor mode) bit rather than the MMCR0_FCS
      (freeze counters in supervisor mode) bit.
      
      This checks the MSR.HV bit at startup, and if it is set, we set the
      freeze_counters_kernel variable to MMCR0_FCHV (it was initialized to
      MMCR0_FCS).  We then use that whenever we need to exclude kernel events.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d095cd46
  3. 18 2月, 2009 21 次提交
  4. 17 2月, 2009 6 次提交
  5. 16 2月, 2009 9 次提交
  6. 15 2月, 2009 2 次提交