1. 30 8月, 2017 2 次提交
  2. 29 8月, 2017 2 次提交
  3. 08 8月, 2017 1 次提交
    • M
      MIPS: PCI: Fix smp_processor_id() in preemptible · 73530266
      Matt Redfearn 提交于
      Commit 1c3c5eab ("sched/core: Enable might_sleep() and
      smp_processor_id() checks early") enables checks for might_sleep() and
      smp_processor_id() being used in preemptible code earlier in the boot
      than before. This results in a new BUG from
      pcibios_set_cache_line_size().
      
      BUG: using smp_processor_id() in preemptible [00000000] code:
      swapper/0/1 caller is pcibios_set_cache_line_size+0x10/0x70
      CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc1-00007-g3ce3e4ba4275 #615
      Stack: 0000000000000000 ffffffff81189694 0000000000000000 ffffffff81822318
             000000000000004e 0000000000000001 800000000e20bd08 20c49ba5e3540000
             0000000000000000 0000000000000000 ffffffff818d0000 0000000000000000
             0000000000000000 ffffffff81189328 ffffffff818ce692 0000000000000000
             0000000000000000 ffffffff81189bc8 ffffffff818d0000 0000000000000000
             ffffffff81828907 ffffffff81769970 800000020ec78d80 ffffffff818c7b48
             0000000000000001 0000000000000001 ffffffff818652b0 ffffffff81896268
             ffffffff818c0000 800000020ec7fb40 800000020ec7fc58 ffffffff81684cac
             0000000000000000 ffffffff8118ab50 0000000000000030 ffffffff81769970
             0000000000000001 ffffffff81122a58 0000000000000000 0000000000000000 ...
      Call Trace:
      [<ffffffff81122a58>] show_stack+0x90/0xb0
      [<ffffffff81684cac>] dump_stack+0xac/0xf0
      [<ffffffff813f7050>] check_preemption_disabled+0x120/0x128
      [<ffffffff818855e8>] pcibios_set_cache_line_size+0x10/0x70
      [<ffffffff81100578>] do_one_initcall+0x48/0x140
      [<ffffffff81865dc4>] kernel_init_freeable+0x194/0x24c
      [<ffffffff8169c534>] kernel_init+0x14/0x118
      [<ffffffff8111ca84>] ret_from_kernel_thread+0x14/0x1c
      
      Fix this by using the cpu_*cache_line_size() macros instead. These
      macros are the "proper" way to determine the CPU cache sizes.
      This makes use of the newly added cpu_tcache_line_size.
      
      Fixes: 1c3c5eab ("sched/core: Enable might_sleep() and smp_processor_id() checks early")
      Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
      Suggested-by: NJames Hogan <james.hogan@imgtec.com>
      Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      73530266
  4. 04 8月, 2017 1 次提交
    • L
      MIPS: PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks · 04c81c72
      Lorenzo Pieralisi 提交于
      The pci_fixup_irqs() function allocates IRQs for all PCI devices present in
      a system; those PCI devices possibly belong to different PCI bus trees (and
      possibly rooted at different host bridges) and may well be enabled (ie
      probed and bound to a driver) by the time pci_fixup_irqs() is called when
      probing a given host bridge driver.
      
      Furthermore, current kernel code relying on pci_fixup_irqs() to assign
      legacy PCI IRQs to devices does not work at all for hotplugged devices in
      that the code carrying out the IRQ fixup is called at host bridge driver
      probe time, which just cannot take into account devices hotplugged after
      the system has booted.
      
      The introduction of map/swizzle function hooks in struct pci_host_bridge
      allows us to define per-bridge map/swizzle functions, that can be used at
      device probe time in PCI core code to allocate IRQs for a given device
      (through pci_assign_irq()).
      
      Convert PCI host bridge initialization code to the
      pci_scan_root_bus_bridge() API (that allows to pass a struct
      pci_host_bridge with initialized map/swizzle pointers) and remove the
      pci_fixup_irqs() call from arch code.
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@imgtec.com>
      04c81c72
  5. 01 8月, 2017 1 次提交
  6. 19 5月, 2017 1 次提交
    • B
      MIPS: PCI: Remove unused busn_offset · 7ee214b5
      Bjorn Helgaas 提交于
      pci_add_resource_offset() is for host bridge windows where the bridge
      translates CPU addresses to PCI bus addresses by adding an offset.  To my
      knowledge, no host bridge translates bus numbers, so this is only useful
      for MEM and IO windows.  In any event, host->busn_offset is never set to
      anything other than zero, so pci_add_resource() is sufficient.
      
      a2e50f53 ("MIPS: PCI: Add a hook for IORESOURCE_BUS in
      pci_controller/bridge_controller") also added busn_resource itself.  This
      is currently unused but may be used by future SGI IP27 fixes, so I left it
      there.
      
      Tested-by: Joshua Kinard <kumba@gentoo.org>	# SGI IP30 and IP27
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NJoshua Kinard <kumba@gentoo.org>
      7ee214b5
  7. 20 4月, 2017 2 次提交
  8. 13 4月, 2017 1 次提交
  9. 10 4月, 2017 1 次提交
  10. 25 1月, 2017 1 次提交
  11. 03 1月, 2017 1 次提交
  12. 07 10月, 2016 3 次提交
    • P
      MIPS: Sanitise coherentio semantics · f2302023
      Paul Burton 提交于
      The coherentio variable has previously been used as a boolean value,
      indicating whether the user specified that coherent I/O should be
      enabled or disabled. It failed to take into account the case where the
      user does not specify any preference, in which case it makes sense that
      we should default to coherent I/O if the hardware supports it
      (hw_coherentio is non-zero).
      
      Introduce an enum to clarify the 3 different values of coherentio & use
      it throughout the code, modifying plat_device_is_coherent() &
      r4k_cache_init() to take into account the default case.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Paul Burton <paul.burton@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/14347/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f2302023
    • P
      MIPS: PCI: Support generic drivers · 87dd9a4d
      Paul Burton 提交于
      Introduce support for PCI drivers using only functionality provided
      generically by the PCI subsystem, by adding the minimum arch-provided
      functions required.
      
      The driver this has been developed for & tested with the xilinx-pcie on
      a MIPS Boston development board.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14346/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      87dd9a4d
    • P
      MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY · c5611df9
      Paul Burton 提交于
      Introduce 2 Kconfig symbols, CONFIG_PCI_DRIVERS_GENERIC &
      CONFIG_PCI_DRIVERS_LEGACY, which indicate whether the system should be
      built to for PCI drivers using the MIPS-specific struct pci_controller
      API (hereafter "legacy" drivers) or more generic drivers using only
      functionality provided by the PCI core (hereafter "generic" drivers).
      
      The Kconfig entries are created such that platforms have to select
      CONFIG_PCI_DRIVERS_GENERIC if they wish to use it - that is, the default
      is CONFIG_PCI_DRIVERS_LEGACY so that existing platforms need no
      modification.
      
      The functions declared in pci.h are rearranged with those provided only
      by pci-legacy.c being guarded by an #ifdef CONFIG_PCI_DRIVERS_LEGACY to
      ensure they are only used in configurations where they are implemented.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14345/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c5611df9
  13. 06 10月, 2016 5 次提交
  14. 05 10月, 2016 1 次提交
    • P
      MIPS: pci: Audit and remove any unnecessary uses of module.h · 2722090a
      Paul Gortmaker 提交于
      Historically a lot of these existed because we did not have
      a distinction between what was modular code and what was providing
      support to modules via EXPORT_SYMBOL and friends.  That changed
      when we forked out support for the latter into the export.h file.
      
      This means we should be able to reduce the usage of module.h
      in code that is obj-y Makefile or bool Kconfig.  The advantage
      in doing so is that module.h itself sources about 15 other headers;
      adding significantly to what we feed cpp, and it can obscure what
      headers we are effectively using.
      
      Since module.h was the source for init.h (for __init) and for
      export.h (for EXPORT_SYMBOL) we consider each obj-y/bool instance
      for the presence of either and replace as needed.
      
      We also needed to remove the no-op MODULE_DEVICE_TABLE usage in
      several instances to permit removal of the module.h include.  The
      files in these instances were all controlled by bool Kconfig.
      
      In one instance, module_param was being used so we transition the
      module.h include onto a moduleparam.h include.
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14035/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      2722090a
  15. 04 10月, 2016 2 次提交
  16. 24 6月, 2016 1 次提交
    • B
      MIPS/PCI: Claim bus resources on PCI_PROBE_ONLY set-ups · 04613617
      Bjorn Helgaas 提交于
      We claim PCI BAR and bridge window resources in pci_bus_assign_resources(),
      but when PCI_PROBE_ONLY is set, we treat those resources as immutable and
      don't call pci_bus_assign_resources(), so the resources aren't put in the
      resource tree.
      
      When the resources aren't in the tree, they don't show up in /proc/iomem,
      we can't detect conflicts, and we need special cases elsewhere for
      PCI_PROBE_ONLY or resources without a parent pointer.
      
      Claim all PCI BAR and window resources in the PCI_PROBE_ONLY case.
      
      If a PCI_PROBE_ONLY platform assigns conflicting resources, Linux can't fix
      the conflicts.  Previously we didn't notice the conflicts, but now we will,
      which may expose new failures.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      04613617
  17. 18 6月, 2016 1 次提交
    • B
      PCI: Unify pci_resource_to_user() declarations · 8221a013
      Bjorn Helgaas 提交于
      Replace the pci_resource_to_user() declarations in each arch that defines
      HAVE_ARCH_PCI_RESOURCE_TO_USER with a single one in linux/pci.h.
      
      Change the MIPS static inline implementation to a non-inline version so the
      static inline doesn't conflict with the new non-static linux/pci.h
      declaration.
      
      No functional change intended.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      8221a013
  18. 28 5月, 2016 1 次提交
  19. 13 5月, 2016 3 次提交
  20. 12 3月, 2016 2 次提交
    • B
      MIPS: Loongson 3: Keep CPU physical (not virtual) addresses in shadow ROM resource · 97f47e73
      Bjorn Helgaas 提交于
      Loongson 3 used the IORESOURCE_ROM_COPY flag for its ROM resource.  There
      are two problems with this:
      
        - When IORESOURCE_ROM_COPY is set, pci_map_rom() assumes the resource
          contains virtual addresses, so it doesn't ioremap the resource.  This
          implies loongson_sysconf.vgabios_addr is a virtual address.  That's a
          problem because resources should contain CPU *physical* addresses not
          virtual addresses.
      
        - When IORESOURCE_ROM_COPY is set, pci_cleanup_rom() calls kfree() on the
          resource.  We did not kmalloc() the loongson_sysconf.vgabios_addr area,
          so it is incorrect to kfree() it.
      
      If we're using a shadow copy in RAM for the Loongson 3 VGA BIOS area,
      disable the ROM BAR and release the address space it was consuming.
      
      Use IORESOURCE_ROM_SHADOW instead of IORESOURCE_ROM_COPY.  This means the
      struct resource contains CPU physical addresses, and pci_map_rom() will
      ioremap() it as needed.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      97f47e73
    • B
      MIPS: Loongson 3: Use temporary struct resource * to avoid repetition · 53f0a509
      Bjorn Helgaas 提交于
      Use a temporary struct resource pointer to avoid needless repetition of
      "pdev->resource[PCI_ROM_RESOURCE]".  No functional change intended.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      53f0a509
  21. 10 2月, 2016 1 次提交
  22. 20 1月, 2016 1 次提交
  23. 22 12月, 2015 1 次提交
  24. 28 11月, 2015 1 次提交
  25. 11 11月, 2015 1 次提交
    • J
      MIPS: pci-rt3883: drop unneeded of_node_get · 972cfd55
      Julia Lawall 提交于
      for_each_child_of_node performs an of_node_get on each iteration, so no
      of_node_get is needed on breaking out of the loop when the device_node
      structure is saved in another variable.
      
      A simplified semantic match that finds this problem is as follows
      (http://coccinelle.lip6.fr):
      
      // <smpl>
      @@
      expression root;
      local idexpression child;
      @@
      
       for_each_child_of_node(root, child) {
         ...
      *  of_node_get(child)
         ...
         break;
       }
      // </smpl>
      Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
      Cc: kernel-janitors@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
      Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Patchwork: https://patchwork.linux-mips.org/patch/11357/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      972cfd55
  26. 16 9月, 2015 2 次提交
    • T
      genirq: Remove irq argument from irq flow handlers · bd0b9ac4
      Thomas Gleixner 提交于
      Most interrupt flow handlers do not use the irq argument. Those few
      which use it can retrieve the irq number from the irq descriptor.
      
      Remove the argument.
      
      Search and replace was done with coccinelle and some extra helper
      scripts around it. Thanks to Julia for her help!
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Julia Lawall <Julia.Lawall@lip6.fr>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      bd0b9ac4
    • B
      PCI: Revert "PCI: Call pci_read_bridge_bases() from core instead of arch code" · 237865f1
      Bjorn Helgaas 提交于
      Revert dff22d20 ("PCI: Call pci_read_bridge_bases() from core instead
      of arch code").
      
      Reading PCI bridge windows is not arch-specific in itself, but there is PCI
      core code that doesn't work correctly if we read them too early.  For
      example, Hannes found this case on an ARM Freescale i.mx6 board:
      
        pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
        pci 0000:00:00.0: PCI bridge to [bus 01-ff]
        pci 0000:00:00.0: BAR 8: no space for [mem size 0x01000000] (mem window)
        pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00200000]
        pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x00004000]
        pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00000100]
      
      The 00:00.0 mem window needs to be at least 3MB: the 01:00.0 device needs
      0x204100 of space, and mem windows are megabyte-aligned.
      
      Bus sizing can increase a bridge window size, but never *decrease* it (see
      d65245c3 ("PCI: don't shrink bridge resources")).  Prior to
      dff22d20, ARM didn't read bridge windows at all, so the "original size"
      was zero, and we assigned a 3MB window.
      
      After dff22d20, we read the bridge windows before sizing the bus.  The
      firmware programmed a 16MB window (size 0x01000000) in 00:00.0, and since
      we never decrease the size, we kept 16MB even though we only needed 3MB.
      But 16MB doesn't fit in the host bridge aperture, so we failed to assign
      space for the window and the downstream devices.
      
      I think this is a defect in the PCI core: we shouldn't rely on the firmware
      to assign sensible windows.
      
      Ray reported a similar problem, also on ARM, with Broadcom iProc.
      
      Issues like this are too hard to fix right now, so revert dff22d20.
      Reported-by: NHannes <oe5hpm@gmail.com>
      Reported-by: NRay Jui <rjui@broadcom.com>
      Link: http://lkml.kernel.org/r/CAAa04yFQEUJm7Jj1qMT57-LG7ZGtnhNDBe=PpSRa70Mj+XhW-A@mail.gmail.com
      Link: http://lkml.kernel.org/r/55F75BB8.4070405@broadcom.comSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NYinghai Lu <yinghai@kernel.org>
      Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      237865f1