This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: martin.blumenstingl@googlemail.com
Cc: john@phrozen.org
Cc: andy.shevchenko@gmail.com
Cc: p.zabel@pengutronix.de
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17127/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Compared to the old xrx200_phy_fw driver the new version has multiple
enhancements. The name of the firmware files does not have to be added
to all .dts files anymore - one now configures the GPHY mode (FE or GE)
instead. Each GPHY can now also boot separate firmware (thus mixing of
GE and FE GPHYs is now possible).
The new implementation is based on the RCU syscon-mfd and uses the
reeset_controller framework instead of raw RCU register reads/writes.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: john@phrozen.org
Cc: p.zabel@pengutronix.de
Cc: kishon@ti.com
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17128/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Instead of hacking the configuration of the FPI bus into the arch code
add an own bus driver for this internal bus. The FPI bus is the main
bus of the SoC. This bus driver makes sure the bus is configured
correctly before the child drivers are getting initialized. This driver
will probably also be used on different SoCs later.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Cc: john@phrozen.org
Cc: p.zabel@pengutronix.de
Cc: kishon@ti.com
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17122/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Commit 08b3c894 ("MIPS: lantiq: Disable xbar fpi burst mode")
accidentally requested the resources from the pmu address region
instead of the xbar registers region, but the check for the return
value of request_mem_region() was wrong. Commit 98ea51cb ("MIPS:
Lantiq: Fix another request_mem_region() return code check") fixed the
check of the return value of request_mem_region() which made the kernel
panics.
This patch now makes use of the correct memory region for the cross bar.

Fixes: 08b3c894 ("MIPS: lantiq: Disable xbar fpi burst mode")
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Cc: John Crispin <john@phrozen.org>
Cc: james.hogan@imgtec.com
Cc: arnd@arndb.de
Cc: sergei.shtylyov@cogentembedded.com
Cc: john@phrozen.org
Cc: <stable@vger.kernel.org> # 4.4.x-
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15751Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Disabling ethernet during reboot (only to enable it again when the
ethernet driver attaches) can put the chip into a faulty state where it
corrupts the header of all incoming packets.

This happens if packets arrive during the time window where the core is
disabled, and it can be easily reproduced by rebooting while sending a
flood ping to the broadcast address.

Fixes: 95135bfa ("MIPS: Lantiq: Deactivate most of the devices by default")
Signed-off-by: NFelix Fietkau <nbd@nbd.name>
Acked-by: NJohn Crispin <john@phrozen.org>
Cc: hauke.mehrtens@lantiq.com
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.4.x-
Patchwork: https://patchwork.linux-mips.org/patch/15078/Signed-off-by: NJames Hogan <james.hogan@imgtec.com>

Hauke already fixed a couple of them, but one instance remains
that checks for a negative integer when it should check
for a NULL pointer:

arch/mips/lantiq/xway/sysctrl.c: In function 'ltq_soc_init':
arch/mips/lantiq/xway/sysctrl.c:473:19: error: ordered comparison of pointer with integer zero [-Werror=extra]

Fixes: 6e807852 ("MIPS: Lantiq: Fix check for return value of request_mem_region()")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15043/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The old address is no longer valid. Use the my new one instead.
Signed-off-by: NJohn Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13201/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11458/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

request_mem_region() returns a pointer and not an integer with an error
value. A check for "< 0" on a pointer will cause problems, replace it
with not null checks instead. This was found with sparse.
Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11395/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11393/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11392/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11391/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11388/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This adds the PUM bits for USB and SDIO devices
Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11387/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

When the SoC starts up most of the devices should be deactivated by the
PMU, they should be activated when they get used by their drivers. Some
devices should not get deactivate at startup like the serial, register
them in a special way.
Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11386/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This adds support for setting the PMU register on the AR10 and GRX390.
Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11382/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The PMU register are accessed in a non atomic way and they could be
accessed by different threads simultaneously, which could cause
problems this patch adds locking around the PMU registers. In
addition we now also wait till the PMU is actually deactivated.

[ralf@linux-mips.org: Fix spelling mistake in commit message as noticed
by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>.]
Signed-off-by: NHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11381/
Patchwork: https://patchwork.linux-mips.org/patch/11396/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch fix spelling typo in printk.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Explicitly enable the clock gate of the internal GPHYs found on xrx200.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/

The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4815/

"nodes" is written with a single "s"
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4814/

Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4521

The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/

Previously we relied on the bootloader to have enabled this bit. However some
bootloaders seem to not enable this for us.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4120/

The XRX200 based SoC have a different register offset for the interface
clock and PCI control registers. This patch detects the SoC and sets the
register offset at runtime. This make PCI work on the VR9 SoC.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4113/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Now that all drivers are converted to OF we are able to remove some remaining
pieces of orphaned code.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3841/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch unifies all clock generation and gating code into one file.
All drivers will now be able to request their clocks via their device.
This patch also adds support for the clockout feature, which allows
clock generation on external pins.

Support for COMMON_CLK will be provided in the next series.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3804/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>