- 04 9月, 2017 1 次提交
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由 Paul Burton 提交于
In preparation for removing the gic_present global variable, switch to using the mips_gic_present() function instead. For the most part this is a straightforward substitution. In cases which previously wrapped the GIC case in an #ifdef CONFIG_MIPS_GIC that #ifdef has been removed, since mips_gic_present() will return a compile-time constant false allowing the affected code to be optimised out anyway. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17044/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 8月, 2017 2 次提交
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由 Paul Burton 提交于
Allow the boot_secondary SMP op to return an error to __cpu_up(), which will in turn return it to its caller. This will allow SMP implementations to return errors quickly in cases they they know have failed, rather than relying upon __cpu_up() eventually timing out waiting for the cpu_running completion. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17014/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
We currently have fields in struct cpuinfo_mips for the core & VP(E) ID of a particular CPU, and various pieces of code directly access those fields. This patch abstracts such access by introducing accessor functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id() and having code that needs to access these values call those functions rather than directly accessing the struct cpuinfo_mips fields. This prepares us for changes to the way in which those values are stored in later patches. The cpu_vpe_id() function is introduced even though we already had a cpu_vpe_id() macro for a couple of reasons: 1) It's more consistent with the core, and future cluster, accessors. 2) It ensures a sensible return type without explicit casts. 3) It's generally preferable to use functions rather than macros. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17009/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 8月, 2017 1 次提交
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由 Matt Redfearn 提交于
smp_ops providers do not modify their ops structures, so they should be made const for robustness. Since currently the MIPS kernel is not mapped with memory protection, this does not in itself provide any security benefit, but it still makes sense to make this change. There are also slight code size efficincies from the structure being made read-only, saving 128 bytes of kernel text on a pistachio_defconfig. Before: text data bss dec hex filename 7187239 1772752 470224 9430215 8fe4c7 vmlinux After: text data bss dec hex filename 7187111 1772752 470224 9430087 8fe447 vmlinux Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: Bart Van Assche <bart.vanassche@sandisk.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Doug Ledford <dledford@redhat.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Joe Perches <joe@perches.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Steven J. Hill <steven.hill@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16784/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 13 4月, 2017 1 次提交
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由 Paul Burton 提交于
Remove the smp-mt IPI code that supported single-core multithreaded systems and instead make use of the IPI IRQ domain support provided by the MIPS CPU interrupt controller driver. This removes some less than nice code, the horrible split between arch & board code and the duplication that led to within board code. The lantiq portion of this patch has only been compile tested. Malta has been tested & is functional. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15837/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 08 3月, 2017 1 次提交
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由 Arnd Bergmann 提交于
After the split of linux/sched.h, several platforms in arch/mips stopped building. Add the respective additional #include statements to fix the problem I first tried adding these into asm/processor.h, but ran into circular header dependencies with that which I could not figure out. The commit I listed as causing the problem is the branch merge, as there is likely a combination of multiple patches in that branch. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Fixes: 1827adb1 ("Merge branch 'WIP.sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip") Link: http://lkml.kernel.org/r/20170308072931.3836696-1-arnd@arndb.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
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- 04 10月, 2016 1 次提交
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由 Matt Redfearn 提交于
The addition of VPE information to /proc/cpuinfo used to be in smp-mt.c. This file is not used by MIPS r6 kernels, so the Virtual Processor information was not present for these CPU types. Move the code to print VPE information into proc.c, add a case for MIPS r6 CPUS, and remove the block from smp-mt.c. Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13847/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 25 2月, 2016 1 次提交
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由 Qais Yousef 提交于
This commit does several things to avoid breaking bisectability. 1- Remove IPI init code from irqchip/mips-gic 2- Implement the new irqchip->send_ipi() in irqchip/mips-gic 3- Select GENERIC_IRQ_IPI Kconfig symbol for MIPS_GIC 4- Change MIPS SMP to use the generic IPI implementation Only the SMP variants that use GIC were converted as it's the only irqchip that will have the support for generic IPI for now. Signed-off-by: NQais Yousef <qais.yousef@imgtec.com> Acked-by: NRalf Baechle <ralf@linux-mips.org> Cc: <jason@lakedaemon.net> Cc: <marc.zyngier@arm.com> Cc: <jiang.liu@linux.intel.com> Cc: <linux-mips@linux-mips.org> Cc: <lisa.parratt@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Link: http://lkml.kernel.org/r/1449580830-23652-18-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 05 3月, 2015 1 次提交
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由 Rusty Russell 提交于
Thanks to spatch, plus manual removal of "&*". Then a sweep for for_each_cpu_mask => for_each_cpu. Signed-off-by: NRusty Russell <rusty@rustcorp.com.au> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org
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- 16 1月, 2015 1 次提交
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由 James Hogan 提交于
Commit 18743d27 ("irqchip: mips-gic: Stop using per-platform mapping tables") in v3.19-rc1 changed the routing of IPIs through the GIC to go to the HW0 IRQ pin along with the rest of the GIC interrupts, rather than to HW1 and HW2 pins. This breaks SMP boot using the CMP or MT SMP implementations because HW0 doesn't get unmasked when secondary CPUs are initialised so the IPIs will never interrupt secondary CPUs (nor any other interrupts routed through the GIC). Commit ff1e29ad ("MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs") fixed this in advance for the CPS SMP implementation by unmasking all hardware interrupt lines for secondary CPUs, so lets do the same for the CMP and MT implementations. Fixes: 18743d27 ("irqchip: mips-gic: Stop using per-platform mapping tables") Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9025/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 24 11月, 2014 2 次提交
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由 Andrew Bresticker 提交于
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrew Bresticker 提交于
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 02 8月, 2014 1 次提交
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由 James Hogan 提交于
Commit d6d3c9af (MIPS: MT: proc: Add support for printing VPE and TC ids) causes a link error when CONFIG_PROC_FS=n: arch/mips/built-in.o: In function `proc_cpuinfo_notifier_init': smp-mt.c: undefined reference to `register_proc_cpuinfo_notifier' This is fixed by adding an ifdef around the procfs handling code in smp-mt.c. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reported-by: NMarkos Chandras <markos.chandras@imgtec.com> Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # >= 3.15 Patchwork: https://patchwork.linux-mips.org/patch/7244/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 27 5月, 2014 1 次提交
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由 Ralf Baechle 提交于
Nothing was using the method and there isn't any need for this hook. This leaves smp_cpus_done() empty for the moment. As suggested by Paul Bolle <pebolle@tiscali.nl>. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 01 4月, 2014 2 次提交
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由 Paul Burton 提交于
Rather than duplicating the GIC IPI send function, share the one already used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6653/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6066/
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- 23 1月, 2014 2 次提交
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由 Steven J. Hill 提交于
If GIC is present, then use it to send IPIs between the cores. Using GIC for IPIs is simpler and is usable for multicore systems compared to the existing way of doing IPIs where all VPEs had to be disabled for another VPE to access the Cause register in one of the TCs and enable all the VPEs back. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Signed-off-by: NJohn Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6040/
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由 Markos Chandras 提交于
According to Documentation/cpu-hotplug.txt, the cpu_present_mask should contain all the CPUs which are present in the system. Therefore, all the TCs currently present in the system should be marked as 'present' even if they will never be brought online. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Signed-off-by: NJohn Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6039/
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- 15 7月, 2013 1 次提交
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由 Paul Gortmaker 提交于
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 5月, 2013 1 次提交
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由 Steven J. Hill 提交于
Move the global variable 'gic_present' to be defined in the file 'arch/mips/kernel/irq-gic.c' instead of defining it individually for each platform making use of the GIC. Also change the type to be an unsigned integer instead of signed. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
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- 01 2月, 2013 1 次提交
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由 Ralf Baechle 提交于
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 23 8月, 2012 1 次提交
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由 Anoop P A 提交于
VSMP kernel build for non-malta platforms fails with following error LD init/built-in.o LD .tmp_vmlinux1 arch/mips/built-in.o: In function `vsmp_init_secondary': smp-mt.c:(.cpuinit.text+0x23cc): undefined reference to `gic_present' smp-mt.c:(.cpuinit.text+0x23d0): undefined reference to `gic_present' make: *** [.tmp_vmlinux1] Error 1 gic_present variable is declared only if IRQ_GIC is selected. Signed-off-by: NAnoop P A <anoop.pa@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/2039/Signed-off-by: NJohn Crispin <blogic@openwrt.org>
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- 29 3月, 2012 1 次提交
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由 David Howells 提交于
Disintegrate asm/system.h for MIPS. Signed-off-by: NDavid Howells <dhowells@redhat.com> Acked-by: NRalf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
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- 27 7月, 2011 1 次提交
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由 Arun Sharma 提交于
This allows us to move duplicated code in <asm/atomic.h> (atomic_inc_not_zero() for now) to <linux/atomic.h> Signed-off-by: NArun Sharma <asharma@fb.com> Reviewed-by: NEric Dumazet <eric.dumazet@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Miller <davem@davemloft.net> Cc: Eric Dumazet <eric.dumazet@gmail.com> Acked-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 31 3月, 2011 1 次提交
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由 Lucas De Marchi 提交于
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>
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- 17 12月, 2010 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 24 9月, 2009 2 次提交
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由 Rusty Russell 提交于
Use the accessors rather than frobbing bits directly (the new versions are const). Signed-off-by: NRusty Russell <rusty@rustcorp.com.au> Signed-off-by: NMike Travis <travis@sgi.com>
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由 Rusty Russell 提交于
We're weaning the core code off handing cpumask's around on-stack. This introduces arch_send_call_function_ipi_mask(), and by defining it, the old arch_send_call_function_ipi is defined by the core code. We also take the chance to wean the implementations off the obsolescent for_each_cpu_mask(): making send_ipi_mask take the pointer seemed the most natural way to ensure all implementations used for_each_cpu. Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>
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- 13 12月, 2008 1 次提交
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由 Rusty Russell 提交于
Impact: cleanup Each SMP arch defines these themselves. Move them to a central location. Twists: 1) Some archs (m32, parisc, s390) set possible_map to all 1, so we add a CONFIG_INIT_ALL_POSSIBLE for this rather than break them. 2) mips and sparc32 '#define cpu_possible_map phys_cpu_present_map'. Those archs simply have phys_cpu_present_map replaced everywhere. 3) Alpha defined cpu_possible_map to cpu_present_map; this is tricky so I just manipulate them both in sync. 4) IA64, cris and m32r have gratuitous 'extern cpumask_t cpu_possible_map' declarations. Signed-off-by: NRusty Russell <rusty@rustcorp.com.au> Reviewed-by: NGrant Grundler <grundler@parisc-linux.org> Tested-by: NTony Luck <tony.luck@intel.com> Acked-by: NIngo Molnar <mingo@elte.hu> Cc: Mike Travis <travis@sgi.com> Cc: ink@jurassic.park.msu.ru Cc: rmk@arm.linux.org.uk Cc: starvik@axis.com Cc: tony.luck@intel.com Cc: takata@linux-m32r.org Cc: ralf@linux-mips.org Cc: grundler@parisc-linux.org Cc: paulus@samba.org Cc: schwidefsky@de.ibm.com Cc: lethal@linux-sh.org Cc: wli@holomorphy.com Cc: davem@davemloft.net Cc: jdike@addtoit.com Cc: mingo@redhat.com
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- 29 4月, 2008 2 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chris Dearman 提交于
It is not being used by Malta and shouldn't be needed for MIPSsim. Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 1月, 2008 2 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 10月, 2007 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 27 8月, 2007 1 次提交
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由 Ralf Baechle 提交于
MIPS doesn't do CPU hotplugging yet but since many of the functions don't even have an __init let's fix this right. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 04 7月, 2007 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 15 6月, 2007 1 次提交
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由 Chris Dearman 提交于
Support for performance counter overflow interrupt that is on a separate interrupt from the timer. Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 07 2月, 2007 1 次提交
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由 Atsushi Nemoto 提交于
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 11月, 2006 1 次提交
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由 Atsushi Nemoto 提交于
Further incorporation of generic irq framework. Replacing __do_IRQ() by proper flow handler would make the irq handling path a bit simpler and faster. * use generic_handle_irq() instead of __do_IRQ(). * use handle_level_irq for obvious level-type irq chips. * use handle_percpu_irq for irqs marked as IRQ_PER_CPU. * setup .eoi routine for irq chips possibly used with handle_percpu_irq. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 01 11月, 2006 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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