1. 04 9月, 2017 1 次提交
  2. 30 8月, 2017 2 次提交
  3. 29 8月, 2017 1 次提交
    • M
      MIPS: SMP: Constify smp ops · ff2c8252
      Matt Redfearn 提交于
      smp_ops providers do not modify their ops structures, so they should be
      made const for robustness. Since currently the MIPS kernel is not mapped
      with memory protection, this does not in itself provide any security
      benefit, but it still makes sense to make this change.
      
      There are also slight code size efficincies from the structure being
      made read-only, saving 128 bytes of kernel text on a
      pistachio_defconfig.
      Before:
         text	   data	    bss	    dec	    hex	filename
      7187239	1772752	 470224	9430215	 8fe4c7	vmlinux
      After:
         text	   data	    bss	    dec	    hex	filename
      7187111	1772752	 470224	9430087	 8fe447	vmlinux
      Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
      Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
      Cc: Bart Van Assche <bart.vanassche@sandisk.com>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
      Cc: Kevin Cernekee <cernekee@gmail.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Doug Ledford <dledford@redhat.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Joe Perches <joe@perches.com>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Steven J. Hill <steven.hill@cavium.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/16784/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ff2c8252
  4. 13 4月, 2017 1 次提交
  5. 08 3月, 2017 1 次提交
  6. 04 10月, 2016 1 次提交
  7. 25 2月, 2016 1 次提交
  8. 05 3月, 2015 1 次提交
  9. 16 1月, 2015 1 次提交
    • J
      MIPS: smp-mt,smp-cmp: Enable all HW IRQs on secondary CPUs · c3f134fb
      James Hogan 提交于
      Commit 18743d27 ("irqchip: mips-gic: Stop using per-platform mapping
      tables") in v3.19-rc1 changed the routing of IPIs through the GIC to go
      to the HW0 IRQ pin along with the rest of the GIC interrupts, rather
      than to HW1 and HW2 pins.
      
      This breaks SMP boot using the CMP or MT SMP implementations because HW0
      doesn't get unmasked when secondary CPUs are initialised so the IPIs
      will never interrupt secondary CPUs (nor any other interrupts routed
      through the GIC).
      
      Commit ff1e29ad ("MIPS: smp-cps: Enable all hardware interrupts on
      secondary CPUs") fixed this in advance for the CPS SMP implementation by
      unmasking all hardware interrupt lines for secondary CPUs, so lets do
      the same for the CMP and MT implementations.
      
      Fixes: 18743d27 ("irqchip: mips-gic: Stop using per-platform mapping tables")
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9025/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c3f134fb
  10. 24 11月, 2014 2 次提交
  11. 02 8月, 2014 1 次提交
  12. 27 5月, 2014 1 次提交
  13. 01 4月, 2014 2 次提交
  14. 23 1月, 2014 2 次提交
  15. 15 7月, 2013 1 次提交
    • P
      MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code · 078a55fc
      Paul Gortmaker 提交于
      commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
      
      The __cpuinit type of throwaway sections might have made sense
      some time ago when RAM was more constrained, but now the savings
      do not offset the cost and complications.  For example, the fix in
      commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
      is a good example of the nasty type of bugs that can be created
      with improper use of the various __init prefixes.
      
      After a discussion on LKML[1] it was decided that cpuinit should go
      the way of devinit and be phased out.  Once all the users are gone,
      we can then finally remove the macros themselves from linux/init.h.
      
      Note that some harmless section mismatch warnings may result, since
      notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
      and are flagged as __cpuinit  -- so if we remove the __cpuinit from
      the arch specific callers, we will also get section mismatch warnings.
      As an intermediate step, we intend to turn the linux/init.h cpuinit
      related content into no-ops as early as possible, since that will get
      rid of these warnings.  In any case, they are temporary and harmless.
      
      Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
      from asm files.  MIPS is interesting in this respect, because there
      are also uasm users hiding behind their own renamed versions of the
      __cpuinit macros.
      
      [1] https://lkml.org/lkml/2013/5/20/589
      
      [ralf@linux-mips.org: Folded in Paul's followup fix.]
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5494/
      Patchwork: https://patchwork.linux-mips.org/patch/5495/
      Patchwork: https://patchwork.linux-mips.org/patch/5509/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      078a55fc
  16. 09 5月, 2013 1 次提交
  17. 01 2月, 2013 1 次提交
  18. 23 8月, 2012 1 次提交
  19. 29 3月, 2012 1 次提交
  20. 27 7月, 2011 1 次提交
  21. 31 3月, 2011 1 次提交
  22. 17 12月, 2010 1 次提交
  23. 24 9月, 2009 2 次提交
  24. 13 12月, 2008 1 次提交
    • R
      cpumask: centralize cpu_online_map and cpu_possible_map · 98a79d6a
      Rusty Russell 提交于
      Impact: cleanup
      
      Each SMP arch defines these themselves.  Move them to a central
      location.
      
      Twists:
      1) Some archs (m32, parisc, s390) set possible_map to all 1, so we add a
         CONFIG_INIT_ALL_POSSIBLE for this rather than break them.
      
      2) mips and sparc32 '#define cpu_possible_map phys_cpu_present_map'.
         Those archs simply have phys_cpu_present_map replaced everywhere.
      
      3) Alpha defined cpu_possible_map to cpu_present_map; this is tricky
         so I just manipulate them both in sync.
      
      4) IA64, cris and m32r have gratuitous 'extern cpumask_t cpu_possible_map'
         declarations.
      Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>
      Reviewed-by: NGrant Grundler <grundler@parisc-linux.org>
      Tested-by: NTony Luck <tony.luck@intel.com>
      Acked-by: NIngo Molnar <mingo@elte.hu>
      Cc: Mike Travis <travis@sgi.com>
      Cc: ink@jurassic.park.msu.ru
      Cc: rmk@arm.linux.org.uk
      Cc: starvik@axis.com
      Cc: tony.luck@intel.com
      Cc: takata@linux-m32r.org
      Cc: ralf@linux-mips.org
      Cc: grundler@parisc-linux.org
      Cc: paulus@samba.org
      Cc: schwidefsky@de.ibm.com
      Cc: lethal@linux-sh.org
      Cc: wli@holomorphy.com
      Cc: davem@davemloft.net
      Cc: jdike@addtoit.com
      Cc: mingo@redhat.com
      98a79d6a
  25. 29 4月, 2008 2 次提交
  26. 29 1月, 2008 2 次提交
  27. 12 10月, 2007 1 次提交
  28. 27 8月, 2007 1 次提交
  29. 04 7月, 2007 1 次提交
  30. 15 6月, 2007 1 次提交
  31. 07 2月, 2007 1 次提交
    • A
      [MIPS] Define MIPS_CPU_IRQ_BASE in generic header · 97dcb82d
      Atsushi Nemoto 提交于
      The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
      platforms and are same value on most platforms (0 or 16, depends on
      CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
      them customizable.  This will save a few cycle on each CPU interrupt.
      
      A good side effect is removing some dependencies to MALTA in generic
      SMTC code.
      
      Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
      mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
      them might cause some header dependency problem and there seems no
      good reason to customize it.  So currently only VR41XX is using custom
      MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
      
      Testing this patch on those platforms is greatly appreciated.  Thank
      you.
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      97dcb82d
  32. 30 11月, 2006 1 次提交
  33. 01 11月, 2006 1 次提交