Slow down the tRp of Micron NAND flash timing.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Initialize the read buffer content to 0xFF.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

When fetch nand data with non-DMA mode, we should align info->data_size to
32bit, not 8bit.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Acked-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NYeasah Pell <yeasah@comrex.com>
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Acked-by: NEric Miao <eric.miao@marvell.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

1. Driver code where pxa_request_dma() is called will most likely
   reference DMA registers as well,  and it is really unnecessary
   to include pxa-regs.h just for this. Move the definitions into
   <mach/dma.h> and make relevant drivers include it instead of
   <mach/pxa-regs.h>.

2. Introduce DMAC_REGS_VIRT as the virtual address base for these
   DMA registers. This allows later processors to re-use the same
   IP while registers may start at different I/O address.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

The various fields in NDTR{01} are in units of clock ticks minus one, but the
ns2cycle macro mistakenly adds one, inflating the number of clock ticks and
making it impossible to set any of these fields to zero.
Signed-off-by: NMatt Reimer <mreimer@vpop.net>
Signed-off-by: NEric Miao <eric.miao@marvell.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Reads from non-page-aligned addresses were broken because while the
address to read from was correctly written to NDCB*, a full page was
always read. Fix this by ignoring the column and only using the page
address.

I suspect this whole-page behavior is due to the controller's need to
read the entire page in order to generate correct ECC. In the non-ECC
case this could be optimized to use the column address, and to set the
read length to what is being requested rather than the length of an
entire page.
Signed-off-by: NMatt Reimer <mreimer@vpop.net>
Signed-off-by: NEric Miao <eric.miao@marvell.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

STM 2Gb flash is a large-page NAND flash.  Set operations accordingly.
This field is dereferenced without a check in several places resulting in
OOPS.
Signed-off-by: NDenis V. Lunev <den@openvz.org>
Acked-by: NEric Miao <ymiao3@marvell.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Where 'pxa_dma_desc' and 'pxa_{request,free}_dma' are referenced.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Where devices only have one consumer, passing a consumer clock ID
has no real benefit.  Remove it.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Minor patch to help debugging of NAND detection.
Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch moves some attributes out from the platform data into the
dynamically created nand device.   This results into a cleaner interface
and allows to use constant pxa3xx_nand_flash definitions.
Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch marks some attributes as 'const' which are set only once and
never be modified by the driver.  There are some changes in parameter
list and variable declarations too which mark them as 'const'.
Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch adds a MTD_NAND_PXA3xx_BUILTIN configuration variables which
allows to disable usage of builtin flash-type table.  Not enabling this
option saves some space in the generated driver.
Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch adds 'flash' and 'num_flash' attributes to the platform data.
There was added code in the driver to iterate across these attributes in the
detect-flash routine.  This is done similarly to the existing method
which uses a 'builtin_flash_types' field.
Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch moves the exported datastructures from the pxa3xx_nand.c driver
into the <mach/pxa3xx_nand.h> header. This is a plain movement without
any modification of the attributes.

This is the first one of a set of patches which:

 * allows to specify used NAND flash in the platform code and allows to turn
   off the old way to specify NAND characteristics in the driver.  This way did
   not worked well as these characteristics depend on the platform and can not be
   derived from NAND id alone.

   E.g.  some NAND chips share the same ID (e.g.  K9K8G08U0A and K9NBG08U5A) but
   have different timings (which are written in the common driver currently and
   must be modified there).

 * adds 'const' annotations at various places

Further patches will be sent to the mtd-list.
Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NSemun Lee <semun.lee@samsung.com>
Acked-by: NEric Miao <eric.miao@marvell.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NEric Miao <eric.miao@marvell.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

This is preliminary since:

1. It supports only _one_ chip select at the moment. As there is no
   existing platforms available using two chip selects of the NAND
   controller, it shall really not include code for supporting the
   2nd chip select for now, as such code cannot be verified.

2. It resorts to the default and simpliest memory based badblock
   table

3. Only limited types of nand flash are currently supported. Most
   PXA3xx processors come with on-chip NAND flash dies, so there
   isn't much flexibility for other types of NAND.

4. The NAND controller should be configured to detect the device's
   ID, thus making it difficult to use nand_scan_ident() to assist
   the detection process (though it's not impossible)

TODO: fix all the above limitations of cuz :-)
Signed-off-by: Neric miao <eric.miao@marvell.com>
Cc: Sergey Podstavin <spodstavin@ru.mvista.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>