1. 05 9月, 2013 1 次提交
  2. 29 3月, 2012 1 次提交
  3. 27 7月, 2011 1 次提交
  4. 15 12月, 2009 4 次提交
  5. 14 10月, 2009 1 次提交
  6. 08 10月, 2009 1 次提交
    • T
      [IA64] Squeeze ticket locks back into 4 bytes. · 9d40ee20
      Tony Luck 提交于
      Linus pointed out that other people have spent large amounts of time
      and effort to optimize the layout of frequently used structures. Often
      these have embedded locks, and the assumption is that a lock takes
      4 bytes.  Linus also pointed out how to work with the limited options
      for atomic instructions on Itanium.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      9d40ee20
  7. 25 9月, 2009 1 次提交
    • T
      [IA64] implement ticket locks for Itanium · 2c86963b
      Tony Luck 提交于
      Back in January 2008 Nick Piggin implemented "ticket" spinlocks
      for X86 (See commit 314cdbef).
      
      IA64 implementation has a couple of differences because of the
      available atomic operations ... e.g. we have no fetchadd2 instruction
      that operates on a 16-bit quantity so we make ticket locks use
      a 32-bit word for each of the current ticket and now-serving values.
      
      Performance on uncontended locks is about 8% worse than the previous
      implementation, but this seems a good trade for determinism in the
      contended case. Performance impact on macro-level benchmarks is in
      the noise.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      2c86963b
  8. 03 4月, 2009 2 次提交
  9. 02 8月, 2008 1 次提交
    • T
      [IA64] Move include/asm-ia64 to arch/ia64/include/asm · 7f30491c
      Tony Luck 提交于
      After moving the the include files there were a few clean-ups:
      
      1) Some files used #include <asm-ia64/xyz.h>, changed to <asm/xyz.h>
      
      2) Some comments alerted maintainers to look at various header files to
      make matching updates if certain code were to be changed. Updated these
      comments to use the new include paths.
      
      3) Some header files mentioned their own names in initial comments. Just
      deleted these self references.
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      7f30491c
  10. 20 10月, 2007 1 次提交
  11. 01 10月, 2006 1 次提交
    • M
      [PATCH] Directed yield: cpu_relax variants for spinlocks and rw-locks · ef6edc97
      Martin Schwidefsky 提交于
      On systems running with virtual cpus there is optimization potential in
      regard to spinlocks and rw-locks.  If the virtual cpu that has taken a lock
      is known to a cpu that wants to acquire the same lock it is beneficial to
      yield the timeslice of the virtual cpu in favour of the cpu that has the
      lock (directed yield).
      
      With CONFIG_PREEMPT="n" this can be implemented by the architecture without
      common code changes.  Powerpc already does this.
      
      With CONFIG_PREEMPT="y" the lock loops are coded with _raw_spin_trylock,
      _raw_read_trylock and _raw_write_trylock in kernel/spinlock.c.  If the lock
      could not be taken cpu_relax is called.  A directed yield is not possible
      because cpu_relax doesn't know anything about the lock.  To be able to
      yield the lock in favour of the current lock holder variants of cpu_relax
      for spinlocks and rw-locks are needed.  The new _raw_spin_relax,
      _raw_read_relax and _raw_write_relax primitives differ from cpu_relax
      insofar that they have an argument: a pointer to the lock structure.
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      ef6edc97
  12. 09 1月, 2006 1 次提交
  13. 13 12月, 2005 1 次提交
  14. 11 9月, 2005 1 次提交
    • I
      [PATCH] spinlock consolidation · fb1c8f93
      Ingo Molnar 提交于
      This patch (written by me and also containing many suggestions of Arjan van
      de Ven) does a major cleanup of the spinlock code.  It does the following
      things:
      
       - consolidates and enhances the spinlock/rwlock debugging code
      
       - simplifies the asm/spinlock.h files
      
       - encapsulates the raw spinlock type and moves generic spinlock
         features (such as ->break_lock) into the generic code.
      
       - cleans up the spinlock code hierarchy to get rid of the spaghetti.
      
      Most notably there's now only a single variant of the debugging code,
      located in lib/spinlock_debug.c.  (previously we had one SMP debugging
      variant per architecture, plus a separate generic one for UP builds)
      
      Also, i've enhanced the rwlock debugging facility, it will now track
      write-owners.  There is new spinlock-owner/CPU-tracking on SMP builds too.
      All locks have lockup detection now, which will work for both soft and hard
      spin/rwlock lockups.
      
      The arch-level include files now only contain the minimally necessary
      subset of the spinlock code - all the rest that can be generalized now
      lives in the generic headers:
      
       include/asm-i386/spinlock_types.h       |   16
       include/asm-x86_64/spinlock_types.h     |   16
      
      I have also split up the various spinlock variants into separate files,
      making it easier to see which does what. The new layout is:
      
         SMP                         |  UP
         ----------------------------|-----------------------------------
         asm/spinlock_types_smp.h    |  linux/spinlock_types_up.h
         linux/spinlock_types.h      |  linux/spinlock_types.h
         asm/spinlock_smp.h          |  linux/spinlock_up.h
         linux/spinlock_api_smp.h    |  linux/spinlock_api_up.h
         linux/spinlock.h            |  linux/spinlock.h
      
      /*
       * here's the role of the various spinlock/rwlock related include files:
       *
       * on SMP builds:
       *
       *  asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
       *                        initializers
       *
       *  linux/spinlock_types.h:
       *                        defines the generic type and initializers
       *
       *  asm/spinlock.h:       contains the __raw_spin_*()/etc. lowlevel
       *                        implementations, mostly inline assembly code
       *
       *   (also included on UP-debug builds:)
       *
       *  linux/spinlock_api_smp.h:
       *                        contains the prototypes for the _spin_*() APIs.
       *
       *  linux/spinlock.h:     builds the final spin_*() APIs.
       *
       * on UP builds:
       *
       *  linux/spinlock_type_up.h:
       *                        contains the generic, simplified UP spinlock type.
       *                        (which is an empty structure on non-debug builds)
       *
       *  linux/spinlock_types.h:
       *                        defines the generic type and initializers
       *
       *  linux/spinlock_up.h:
       *                        contains the __raw_spin_*()/etc. version of UP
       *                        builds. (which are NOPs on non-debug, non-preempt
       *                        builds)
       *
       *   (included on UP-non-debug builds:)
       *
       *  linux/spinlock_api_up.h:
       *                        builds the _spin_*() APIs.
       *
       *  linux/spinlock.h:     builds the final spin_*() APIs.
       */
      
      All SMP and UP architectures are converted by this patch.
      
      arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
      crosscompilers.  m32r, mips, sh, sparc, have not been tested yet, but should
      be mostly fine.
      
      From: Grant Grundler <grundler@parisc-linux.org>
      
        Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
        Builds 32-bit SMP kernel (not booted or tested).  I did not try to build
        non-SMP kernels.  That should be trivial to fix up later if necessary.
      
        I converted bit ops atomic_hash lock to raw_spinlock_t.  Doing so avoids
        some ugly nesting of linux/*.h and asm/*.h files.  Those particular locks
        are well tested and contained entirely inside arch specific code.  I do NOT
        expect any new issues to arise with them.
      
       If someone does ever need to use debug/metrics with them, then they will
        need to unravel this hairball between spinlocks, atomic ops, and bit ops
        that exist only because parisc has exactly one atomic instruction: LDCW
        (load and clear word).
      
      From: "Luck, Tony" <tony.luck@intel.com>
      
         ia64 fix
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NArjan van de Ven <arjanv@infradead.org>
      Signed-off-by: NGrant Grundler <grundler@parisc-linux.org>
      Cc: Matthew Wilcox <willy@debian.org>
      Signed-off-by: NHirokazu Takata <takata@linux-m32r.org>
      Signed-off-by: NMikael Pettersson <mikpe@csd.uu.se>
      Signed-off-by: NBenoit Boissinot <benoit.boissinot@ens-lyon.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      fb1c8f93
  15. 11 8月, 2005 1 次提交
    • C
      [IA64] Spinlock optimizations · f5210891
      Christoph Lameter 提交于
      1. Nontemporal store for spin unlock.
      
      A nontemporal store will not update the LRU setting for the cacheline. The
      cacheline with the lock may therefore be evicted faster from the cpu
      caches. Doing so may be useful since it increases the chance that the
      exclusive cache line has been evicted when another cpu is trying to
      acquire the lock.
      
      The time between dropping and reacquiring a lock on the same cpu is
      typically very small so the danger of the cacheline being
      evicted is negligible.
      
      2. Avoid semaphore operation in write_unlock and use nontemporal store
      
      write_lock uses a cmpxchg like the regular spin_lock but write_unlock uses
      clear_bit which requires a load and then a loop over a cmpxchg. The
      following patch makes write_unlock simply use a nontemporal store to clear
      the highest 8 bits. We will then still have the lower 3 bytes (24 bits)
      left to count the readers.
      
      Doing the byte store will reduce the number of possible readers from 2^31
      to 2^24 = 16 million.
      
      These patches were discussed already:
      
      http://marc.theaimsgroup.com/?t=111472054400001&r=1&w=2
      http://marc.theaimsgroup.com/?l=linux-ia64&m=111401837707849&w=2
      
      The nontemporal stores will only work using GCC. If a compiler is used
      that does not support inline asm then fallback C code is used. This
      will preserve the byte store but not be able to do the nontemporal stores.
      Signed-off-by: NChristoph Lameter <clameter@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      f5210891
  16. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4