“1717f2096b543cede7a380c858c765c41936bc35”上不存在“include/git@gitcode.net:openeuler/kernel.git”
  1. 07 5月, 2018 3 次提交
  2. 19 2月, 2017 1 次提交
  3. 05 5月, 2015 1 次提交
    • C
      thermal: exynos: Add the support for Exynos5433 TMU · 488c7455
      Chanwoo Choi 提交于
      This patch adds the support for Exynos5433's TMU (Thermal Management Unit).
      Exynos5433 has a little different register bit fields as following description:
      - Support the eight trip points for rising/falling interrupt by using two registers
      - Read the calibration type (1-point or 2-point) and sensor id from TRIMINFO register
      - Use a little different register address
      
      Cc: Zhang Rui <rui.zhang@intel.com>
      Cc: Eduardo Valentin <edubezval@gmail.com>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
      Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
      488c7455
  4. 01 2月, 2015 1 次提交
    • A
      thermal: exynos: Add TMU support for Exynos7 SoC · 6c247393
      Abhilash Kesavan 提交于
      Add registers, bit fields and compatible strings for Exynos7 TMU
      (Thermal Management Unit). Following are a few of the differences
      in the Exynos7 TMU from earlier SoCs:
              - 8 trigger levels
              - Different bit offsets and more registers for the rising
              and falling thresholds.
              - New power down detection bit in the TMU_CONTROL register
              which does not update the CURRENT_TEMP0 when tmu power down
              is detected.
              - Change in bit offset for the NEXT_DATA field of EMUL_CON
              register. EMUL_CON register address has also changed.
              - INTSTAT and INTCLEAR registers present in earlier SoCs
              have been combined into one INTPEND register. The register
              address for INTCLEAR and INTPEND is also different.
              - Since there are 8 rising/falling interrupts as against
              at most 4 in earlier SoCs the INTEN bit offsets are different.
              - Multiple probe support which is handled by a TMU_CONTROL1
              register (No support for this in the current patch).
      
      This patch adds special clock support required only for Exynos7. It
      also updates the "code_to_temp" prototype as Exynos7 has 9 bit
      code-temp mapping.
      Acked-by: NLukasz Majewski <l.majewski@samsung.com>
      Tested-by: NLukasz Majewski <l.majewski@samsung.com>
      Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
      Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
      6c247393
  5. 25 1月, 2015 3 次提交
  6. 20 11月, 2014 26 次提交
  7. 03 11月, 2014 5 次提交
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