- 15 4月, 2014 7 次提交
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由 Nicolin Chen 提交于
By doing this, the driver can drop around 50 lines and become neater. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
Patch ASoC: fsl_sai: Fix buggy configurations in trigger() doesn't entirely fix the condition: FRDE of the current substream direction is being cleared while the code is still using the non-updated one. Thus this patch fixes this issue by checking the opposite one's FRDE alone since the current one's is absolutely disabled. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
The SAI mainly has the following clocks: bus clock control and configure registers and to generate synchronous interrupts and DMA requests. mclk1, mclk2, mclk3 to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. So this patch adds these clocks and their clock controls to the driver. [ To concern the old DTB cases, I've added a bit of extra code to make the driver compatible with them. And by marking clock NULL if failed to get, the clk_prepare() or clk_get_rate() would easily return 0 so no further path should be broken. -- by Nicolin ] Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Acked-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
The next coming i.MX6 Solo X SoC also contains SAI module while we use imp_pcm_init() for i.MX platform. So this patch adds one compatible route for imx6sx and updates the DT doc accordingly. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
We only enable one side interrupt for each stream since over/underrun on the opposite stream would be resulted from what we previously did, enabling TERE but remaining FRDE disabled, even though the xrun on the opposite direction will not break the current stream. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Acked-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
The current trigger() has two crucial problems: 1) The DMA request enabling operations (FSL_SAI_CSR_FRDE) for Tx and Rx are now totally exclusive: It would fail to run simultaneous Tx-Rx cases. 2) The TERE disabling operation depends on an incorrect condition -- active reference count that only gets increased in snd_pcm_open() and decreased in snd_pcm_close(): The TERE would never get cleared. So this patch overwrites the trigger function by following these rules: A) We continue to support tx-async-while-rx-sync-to-tx case alone, which's originally limited by this fsl_sai driver, but we make the code easy to modify for the further support of the opposite case. B) We enable both TE and RE for PLAYBACK stream or CAPTURE stream but only enabling the DMA request bit (FSL_SAI_CSR_FRDE) of the current direction due to the requirement of SAI -- For tx-async-while-rx-sync-to-tx case, the receiver is enabled only when both the transmitter and receiver are enabled. Tested cases: a) aplay test.wav -d5 b) arecord -r44100 -c2 -fS16_LE test.wav -d5 c) arecord -r44100 -c2 -fS16_LE -d5 | aplay d) (aplay test2.wav &); sleep 1; arecord -r44100 -c2 -fS16_LE test.wav -d1 e) (arecord -r44100 -c2 -fS16_LE test.wav -d5 &); sleep 1; aplay test.wav -d1 Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Acked-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
This patch improves fsl_sai_isr() in these ways: 1, Add comment for mask fetching code. 2, Return IRQ_NONE if the IRQ is not for the device. 3, Use regmap_write() instead of regmap_update_bits(). Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 08 4月, 2014 1 次提交
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由 Nicolin Chen 提交于
The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge. However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962. Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Acked-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 27 3月, 2014 1 次提交
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由 Nicolin Chen 提交于
It's quite cricial to clear error flags because SAI might hang if getting FIFO underrun during playback (I haven't confirmed the same issue on Rx overflow though). So this patch enables those irq and adds isr() to clear the flags so as to keep playback entirely safe. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 27 2月, 2014 1 次提交
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由 Xiubo Li 提交于
o Add SND_SOC_DAIFMT_DSP_A support. o Add SND_SOC_DAIFMT_DSP_B support. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 26 2月, 2014 1 次提交
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由 Xiubo Li 提交于
o Fix some bugs of fsl_sai_set_dai_fmt_tr(). o Add SND_SOC_DAIFMT_LEFT_J support. o Add SND_SOC_DAIFMT_CBS_CFM support. o Add SND_SOC_DAIFMT_CBM_CFS support. o And SND_SOC_DAIFMT_RIGHT_J need to be done in the future. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 10 2月, 2014 1 次提交
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由 Xiubo Li 提交于
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 08 1月, 2014 1 次提交
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由 Xiubo Li 提交于
Makes the code slightly shorter. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 31 12月, 2013 2 次提交
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由 Xiubo Li 提交于
Revert the SAI's endianess for fifo data to/from DMA engine. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Xiubo Li 提交于
This is maybe one bug or a limitation of the hardware that the {T,R}CR2's Synchronous Mode bits must be set as late as possible, or the SAI device maybe hanged up, and there has not any explaination about this limitation in the SAI Data Sheet. And the {T,R}CR2's Synchronous Mode bits must be set at the same time whether for Tx or Rx stream. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 30 12月, 2013 2 次提交
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由 Xiubo Li 提交于
Enables/Disables the corresponding data channel for tx/rx operation. A channel must be enabled before its FIFO is accessed, and then disable it when tx/rx is stopped or idle. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Xiubo Li 提交于
Because we cannot make sure which one of _dai_fmt() and _dai_sysclk() will be firstly called. So move the RCSR/TCSR and TCR1/RCR1's initialization to _dai_probe(), and this can make sure that before any of {T,R}CR{1~5} register to be set the RCSR/TCSR's RE/TE bit has been cleared for the hareware limitation. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 21 12月, 2013 9 次提交
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由 Nicolin Chen 提交于
Generally we would write code for local variable like: static new_func() { struct xxx *yyy; ... int ret; } But this driver only follows this pattern for some functions, not all. Thus this patch sorts the local variable in the general way. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
Since using dev_err() there's no need to mention SAI any more, it will print the full name of the driver -- fsl_sai. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
We can save this ret to make the code neater. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
SAi only supports two data channels on hardware level and the driver also does register the min->1 and max->2, so no need to check channels. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
Use common helper function snd_pcm_format_width() to make code neater. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Nicolin Chen 提交于
There are two functions haven't clk_disable_unprepare() if having error. Thus fix them. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Reviewed-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Xiubo Li 提交于
Makes the code slightly shorter Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Xiubo Li 提交于
Makes the code slightly shorter Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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由 Xiubo Li 提交于
There is no need of this function and makes the code slightly shorter Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 19 12月, 2013 1 次提交
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由 Xiubo Li 提交于
This adds Freescale SAI ASoC Audio support. This implementation is only compatible with device tree definition. Features: o Supports playback/capture o Supports 16/20/24 bit PCM o Supports 8k - 96k sample rates o Supports master and slave mode. Signed-off-by: NAlison Wang <b18965@freescale.com> Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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