1. 15 4月, 2014 7 次提交
  2. 08 4月, 2014 1 次提交
    • N
      ASoC: fsl_sai: Fix Bit Clock Polarity configurations · ef33bc32
      Nicolin Chen 提交于
      The BCP bit in TCR4/RCR4 register rules as followings:
        0 Bit clock is active high with drive outputs on rising edge
          and sample inputs on falling edge.
        1 Bit clock is active low with drive outputs on falling edge
          and sample inputs on rising edge.
      
      For all formats currently supported in the fsl_sai driver, they're exactly
      sending data on the falling edge and sampling on the rising edge.
      
      However, the driver clears this BCP bit for all of them which results click
      noise when working with SGTL5000 and big noise with WM8962.
      
      Thus this patch corrects the BCP settings for all the formats here to fix
      the nosie issue.
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Acked-by: NXiubo Li <Li.Xiubo@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      ef33bc32
  3. 27 3月, 2014 1 次提交
  4. 27 2月, 2014 1 次提交
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  6. 10 2月, 2014 1 次提交
  7. 08 1月, 2014 1 次提交
  8. 31 12月, 2013 2 次提交
  9. 30 12月, 2013 2 次提交
  10. 21 12月, 2013 9 次提交
  11. 19 12月, 2013 1 次提交