1. 17 4月, 2008 17 次提交
  2. 07 4月, 2008 1 次提交
  3. 05 4月, 2008 2 次提交
  4. 27 3月, 2008 2 次提交
  5. 22 3月, 2008 1 次提交
  6. 06 3月, 2008 1 次提交
  7. 26 2月, 2008 4 次提交
    • M
      x86: fix boot failure on 486 due to TSC breakage · 12c247a6
      Mikael Pettersson 提交于
       > Diffing dmesg between git7 and git8 doesn't sched any light since
       > git8 also removed the printouts of the x86 caps as they were being
       > initialised and updated. I'm currently adding those printouts back
       > in the hope of seeing where and when the caps get broken.
      
      That turned out to be very illuminating:
      
       --- dmesg-2.6.24-git7	2008-02-24 18:01:25.295851000 +0100
       +++ dmesg-2.6.24-git8	2008-02-24 18:01:25.530358000 +0100
       ...
       CPU: After generic identify, caps: 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      
       CPU: After all inits, caps: 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      +CPU: After applying cleared_cpu_caps, caps: 00000013 00000000 00000000 00000000 00000000 00000000 00000000 00000000
      
      Notice how the TSC cap bit goes from Off to On.
      
      (The first two lines are printout loops from -git7 forward-ported
      to -git8, the third line is the same printout loop added just after
      the xor-with-cleared_cpu_caps[] loop.)
      
      Here's how the breakage occurs:
      1. arch/x86/kernel/tsc_32.c:tsc_init() sees !cpu_has_tsc,
         so bails and calls setup_clear_cpu_cap(X86_FEATURE_TSC).
      2. include/asm-x86/cpufeature.h:setup_clear_cpu_cap(bit) clears
         the bit in boot_cpu_data and sets it in cleared_cpu_caps
      3. arch/x86/kernel/cpu/common.c:identify_cpu() XORs all caps
         in with cleared_cpu_caps
         HOWEVER, at this point c->x86_capability correctly has TSC
         Off, cleared_cpu_caps has TSC On, so the XOR incorrectly
         sets TSC to On in c->x86_capability, with disastrous results.
      
      The real bug is that clearing bits with XOR only works if the
      bits are known to be 1 prior to the XOR, and that's not true here.
      
      A simple fix is to convert the XOR to AND-NOT instead. The following
      patch does that, and allows my 486 to boot 2.6.25-rc kernels again.
      
      [ mingo@elte.hu: fixed a similar bug in setup_64.c as well. ]
      
      The breakage was introduced via commit 7d851c8d.
      Signed-off-by: NMikael Pettersson <mikpe@it.uu.se>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      12c247a6
    • J
      x86: don't print a warning when MTRR are blank and running in KVM · 4147c874
      Joerg Roedel 提交于
      Inside a KVM virtual machine the MTRRs are usually blank. This confuses Linux
      and causes a warning message at boot. This patch removes that warning message
      when running Linux as a KVM guest.
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4147c874
    • R
      x86/mtrr: fix kernel-doc missing notation · f5106d91
      Randy Dunlap 提交于
      Fix mtrr kernel-doc warning:
      Warning(linux-2.6.24-git12//arch/x86/kernel/cpu/mtrr/main.c:677): No description found for parameter 'end_pfn'
      Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f5106d91
    • H
      x86: do not promote TM3x00/TM5x00 to i686-class · a7ef94e6
      H. Peter Anvin 提交于
      We have been promoting Transmeta TM3x00/TM5x00 chips to i686-class
      based on the notion that they contain all the user-space visible
      features of an i686-class chip.  However, this is not actually true:
      they lack the EA-taking long NOPs (0F 1F /0).  Since this is a
      userspace-visible incompatibility, downgrade these CPUs to the
      manufacturer-defined i586 level.
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      a7ef94e6
  8. 19 2月, 2008 1 次提交
  9. 10 2月, 2008 1 次提交
  10. 07 2月, 2008 10 次提交