1. 16 3月, 2013 1 次提交
  2. 16 1月, 2013 1 次提交
  3. 24 10月, 2012 1 次提交
  4. 06 6月, 2012 1 次提交
  5. 20 3月, 2012 1 次提交
    • M
      x86: kvmclock: abstract save/restore sched_clock_state · b74f05d6
      Marcelo Tosatti 提交于
      Upon resume from hibernation, CPU 0's hvclock area contains the old
      values for system_time and tsc_timestamp. It is necessary for the
      hypervisor to update these values with uptodate ones before the CPU uses
      them.
      
      Abstract TSC's save/restore sched_clock_state functions and use
      restore_state to write to KVM_SYSTEM_TIME MSR, forcing an update.
      
      Also move restore_sched_clock_state before __restore_processor_state,
      since the later calls CONFIG_LOCK_STAT's lockstat_clock (also for TSC).
      Thanks to Igor Mammedov for tracking it down.
      
      Fixes suspend-to-disk with kvmclock.
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      b74f05d6
  6. 16 3月, 2012 1 次提交
    • A
      x86, tsc: Skip refined tsc calibration on systems with reliable TSC · 57779dc2
      Alok Kataria 提交于
      While running the latest Linux as guest under VMware in highly
      over-committed situations, we have seen cases when the refined TSC
      algorithm fails to get a valid tsc_start value in
      tsc_refine_calibration_work from multiple attempts. As a result the
      kernel keeps on scheduling the tsc_irqwork task for later. Subsequently
      after several attempts when it gets a valid start value it goes through
      the refined calibration and either bails out or uses the new results.
      Given that the kernel originally read the TSC frequency from the
      platform, which is the best it can get, I don't think there is much
      value in refining it.
      
      So  for systems which get the TSC frequency from the platform we
      should skip the refined tsc algorithm.
      
      We can use the TSC_RELIABLE cpu cap flag to detect this, right now it is
      set only on VMware and for Moorestown Penwell both of which have there
      own TSC calibration methods.
      Signed-off-by: NAlok N Kataria <akataria@vmware.com>
      Cc: John Stultz <johnstul@us.ibm.com>
      Cc: Dirk Brandewie <dirk.brandewie@gmail.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: stable@kernel.org
      [jstultz: Reworked to simply not schedule the refining work,
      rather then scheduling the work and bombing out later]
      Signed-off-by: NJohn Stultz <john.stultz@linaro.org>
      57779dc2
  7. 13 3月, 2012 1 次提交
  8. 18 1月, 2012 1 次提交
    • L
      x86, tsc: Fix SMI induced variation in quick_pit_calibrate() · 68f30fbe
      Linus Torvalds 提交于
      pit_expect_msb() returns success wrongly in the below SMI scenario:
      
      a. pit_verify_msb() has not yet seen the MSB transition.
      
      b. we are close to the MSB transition though and got a SMI immediately after
         returning from pit_verify_msb() which didn't see the MSB transition. PIT MSB
         transition has happened somewhere during SMI execution.
      
      c. returned from SMI and we noted down the 'tsc', saw the pit MSB change now and
         exited the loop to calculate 'deltatsc'. Instead of noting the TSC at the MSB
         transition, we are way off because of the SMI.  And as the SMI happened
         between the pit_verify_msb() and before the 'tsc' is recorded in the
         for loop, 'delattsc' (d1/d2 in quick_pit_calibrate()) will be small and
         quick_pit_calibrate() will not notice this error.
      
      Depending on whether SMI disturbance happens while computing d1 or d2, we will
      see the TSC calibrated value smaller or bigger than the expected value. As a
      result, in a cluster we were seeing a variation of approximately +/- 20MHz in
      the calibrated values, resulting in NTP failures.
      
        [ As far as the SMI source is concerned, this is a periodic SMI that gets
          disabled after ACPI is enabled by the OS. But the TSC calibration happens
          before the ACPI is enabled. ]
      
      To address this, change pit_expect_msb() so that
      
       - the 'tsc' is the TSC in between the two reads that read the MSB
      change from the PIT (same as before)
      
       - the 'delta' is the difference in TSC from *before* the MSB changed
      to *after* the MSB changed.
      
      Now the delta is twice as big as before (it covers four PIT accesses,
      roughly 4us) and quick_pit_calibrate() will loop a bit longer to get
      the calibrated value with in the 500ppm precision. As the delta (d1/d2)
      covers four PIT accesses, actual calibrated result might be closer to
      250ppm precision.
      
      As the loop now takes longer to stabilize, double MAX_QUICK_PIT_MS to 50.
      
      SMI disturbance will showup as much larger delta's and the loop will take
      longer than usual for the result to be with in the accepted precision. Or will
      fallback to slow PIT calibration if it takes more than 50msec.
      
      Also while we are at this, remove the calibration correction that aims to
      get the result to the middle of the error bars. We really don't know which
      direction to correct into, so remove it.
      Reported-and-tested-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Link: http://lkml.kernel.org/r/1326843337.5291.4.camel@sbsiddha-mobl2Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      68f30fbe
  9. 06 12月, 2011 2 次提交
  10. 22 11月, 2011 1 次提交
  11. 15 7月, 2011 1 次提交
  12. 14 7月, 2011 1 次提交
  13. 01 6月, 2011 1 次提交
  14. 24 5月, 2011 4 次提交
  15. 18 3月, 2011 1 次提交
  16. 15 1月, 2011 1 次提交
    • J
      x86: tsc: Fix calibration refinement conditionals to avoid divide by zero · 62627bec
      John Stultz 提交于
      Konrad Wilk reported that the new delayed calibration crashes with a
      divide by zero on Xen. The reason is that Xen sets the pmtimer
      address, but reading from it returns 0xffffff. That results in the
      ref_start and ref_stop value being the same, so the delta is zero
      which causes the divide by zero later in the calculation.
      
      The conditional (!hpet && !ref_start && !ref_stop) which sanity checks
      the calibration reference values doesn't really make sense. If the
      refs are null, but hpet is on, we still want to break out.
      
      The div by zero would be possible to trigger by chance if both reads
      from the hardware provided the exact same value (due to hardware
      wrapping).
      
      So checking if both the ref values are the same should handle if we
      don't have hardware (both null) or if they are the same value (either by
      invalid hardware, or by chance), avoiding the div by zero issue.
      
      [ tglx: Applied the same fix to native_calibrate_tsc() where this
        	check was copied from ]
      Reported-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Tested-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      Signed-off-by: NJohn Stultz <johnstul@us.ibm.com>
      LKML-Reference: <1295024788-15619-1-git-send-email-johnstul@us.ibm.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      62627bec
  17. 11 1月, 2011 1 次提交
  18. 30 12月, 2010 1 次提交
  19. 13 12月, 2010 1 次提交
    • T
      x86: Check tsc available/disabled in the delayed init function · a8760eca
      Thomas Gleixner 提交于
      The delayed TSC init function does not check whether the system has no
      TSC or TSC is disabled at the kernel command line, which results in a
      crash in the work queue based extended calibration due to division by
      zero because the basic calibration never happened.
      
      Add the missing checks and do not touch TSC when not available or
      disabled.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: John Stultz <johnstul@us.ibm.com>
      a8760eca
  20. 03 12月, 2010 1 次提交
    • J
      x86: Improve TSC calibration using a delayed workqueue · 08ec0c58
      John Stultz 提交于
      Boot to boot the TSC calibration may vary by quite a large amount.
      
      While normal variance of 50-100ppm can easily be seen, the quick
      calibration code only requires 500ppm accuracy, which is the limit
      of what NTP can correct for.
      
      This can cause problems for systems being used as NTP servers, as
      every time they reboot it can take hours for them to calculate the
      new drift error caused by the calibration.
      
      The classic trade-off here is calibration accuracy vs slow boot times,
      as during the calibration nothing else can run.
      
      This patch uses a delayed workqueue  to calibrate the TSC over the
      period of a second. This allows very accurate calibration (in my
      tests only varying by 1khz or 0.4ppm boot to boot). Additionally this
      refined calibration step does not block the boot process, and only
      delays the TSC clocksoure registration by a few seconds in early boot.
      If the refined calibration strays 1% from the early boot calibration
      value, the system will fall back to already calculated early boot
      calibration.
      
      Credit to Andi Kleen who suggested using a timer quite awhile back,
      but I dismissed it thinking the timer calibration would be done after
      the clocksource was registered (which would break things). Forgive
      me for my short-sightedness.
      
      This patch has worked very well in my testing, but TSC hardware is
      quite varied so it would probably be good to get some extended
      testing, possibly pushing inclusion out to 2.6.39.
      Signed-off-by: NJohn Stultz <johnstul@us.ibm.com>
      LKML-Reference: <1289003985-29060-1-git-send-email-johnstul@us.ibm.com>
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      CC: Thomas Gleixner <tglx@linutronix.de>
      CC: Ingo Molnar <mingo@elte.hu>
      CC: Martin Schwidefsky <schwidefsky@de.ibm.com>
      CC: Clark Williams <williams@redhat.com>
      CC: Andi Kleen <andi@firstfloor.org>
      08ec0c58
  21. 19 10月, 2010 1 次提交
  22. 11 9月, 2010 2 次提交
  23. 26 8月, 2010 1 次提交
    • B
      x86, tsc: Remove CPU frequency calibration on AMD · acf01734
      Borislav Petkov 提交于
      6b37f5a2 introduced the CPU frequency
      calibration code for AMD CPUs whose TSCs didn't increment with the
      core's P0 frequency. From F10h, revB onward, however, the TSC increment
      rate is denoted by MSRC001_0015[24] and when this bit is set (which
      should be done by the BIOS) the TSC increments with the P0 frequency
      so the calibration is not needed and booting can be a couple of mcecs
      faster on those machines.
      
      Besides, there should be virtually no machines out there which don't
      have this bit set, therefore this calibration can be safely removed. It
      is a shaky hack anyway since it assumes implicitly that the core is in
      P0 when BIOS hands off to the OS, which might not always be the case.
      Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <20100825162823.GE26438@aftab>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      acf01734
  24. 20 8月, 2010 1 次提交
    • S
      x86, tsc, sched: Recompute cyc2ns_offset's during resume from sleep states · cd7240c0
      Suresh Siddha 提交于
      TSC's get reset after suspend/resume (even on cpu's with invariant TSC
      which runs at a constant rate across ACPI P-, C- and T-states). And in
      some systems BIOS seem to reinit TSC to arbitrary large value (still
      sync'd across cpu's) during resume.
      
      This leads to a scenario of scheduler rq->clock (sched_clock_cpu()) less
      than rq->age_stamp (introduced in 2.6.32). This leads to a big value
      returned by scale_rt_power() and the resulting big group power set by the
      update_group_power() is causing improper load balancing between busy and
      idle cpu's after suspend/resume.
      
      This resulted in multi-threaded workloads (like kernel-compilation) go
      slower after suspend/resume cycle on core i5 laptops.
      
      Fix this by recomputing cyc2ns_offset's during resume, so that
      sched_clock() continues from the point where it was left off during
      suspend.
      Reported-by: NFlorian Pritz <flo@xssn.at>
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: <stable@kernel.org> # [v2.6.32+]
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <1282262618.2675.24.camel@sbsiddha-MOBL3.sc.intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      cd7240c0
  25. 27 7月, 2010 1 次提交
  26. 09 2月, 2010 1 次提交
  27. 05 2月, 2010 1 次提交
  28. 18 1月, 2010 1 次提交
  29. 18 12月, 2009 1 次提交
  30. 21 9月, 2009 1 次提交
    • F
      x86: Trivial whitespace cleanups · 878f4f53
      Felipe Contreras 提交于
      Signed-off-by: NFelipe Contreras <felipe.contreras@gmail.com>
      Cc: Vegard Nossum <vegardno@ifi.uio.no>
      Cc: Pekka Enberg <penberg@cs.helsinki.fi>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Alok N Kataria <akataria@vmware.com>
      Cc: "Tan Wei Chong" <wei.chong.tan@intel.com>
      Cc: Len Brown <len.brown@intel.com>
      Cc: Lin Ming <ming.m.lin@intel.com>
      Cc: Bob Moore <robert.moore@intel.com>
      LKML-Reference: <1253137123-18047-2-git-send-email-felipe.contreras@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      878f4f53
  31. 31 8月, 2009 3 次提交
  32. 29 8月, 2009 2 次提交
    • J
      x86: Make tsc=reliable override boot time stability checks · d3b8f889
      john stultz 提交于
      This patch makes the tsc=reliable option disable the boot time
      stability checks. Currently the option only disables the runtime
      watchdog checks. This change allows folks who want to override the
      boot time TSC stability checks and use the TSC when the system would
      otherwise disqualify it.
      
      There still are some situations that the TSC will be disqualified,
      such as cpufreq scaling. But these are situations where the box will
      hang if allowed.
      
      Patch also includes a fix for an issue found by Thomas Gleixner, where
      the TSC disqualification message wouldn't be printed after a call to
      unsynchronized_tsc().
      Signed-off-by: NJohn Stultz <johnstul@us.ibm.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: akataria@vmware.com
      Cc: Stephen Hemminger <shemminger@vyatta.com>
      LKML-Reference: <1250552447.7212.92.camel@localhost.localdomain>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      d3b8f889
    • T
      clocksource: Resolve cpu hotplug dead lock with TSC unstable · 7285dd7f
      Thomas Gleixner 提交于
      Martin Schwidefsky analyzed it:
      To register a clocksource the clocksource_mutex is acquired and if
      necessary timekeeping_notify is called to install the clocksource as
      the timekeeper clock. timekeeping_notify uses stop_machine which needs
      to take cpu_add_remove_lock mutex.
      Starting a new cpu is done with the cpu_add_remove_lock mutex held.
      native_cpu_up checks the tsc of the new cpu and if the tsc is no good
      clocksource_change_rating is called. Which needs the clocksource_mutex
      and the deadlock is complete.
      
      The solution is to replace the TSC via the clocksource watchdog
      mechanism. Mark the TSC as unstable and schedule the watchdog work so
      it gets removed in the watchdog thread context.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      LKML-Reference: <new-submission>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: John Stultz <johnstul@us.ibm.com>
      7285dd7f