1. 14 10月, 2010 1 次提交
    • K
      spi/fsl_spi: Fix compile errors when building on ppc64 · ef6510ba
      Kumar Gala 提交于
      We get the following when building on ppc64 due to lack of include of
      <asm/io.h>:
      
      In file included from drivers/spi/spi_fsl_espi.c:25:0:
      drivers/spi/spi_fsl_lib.h: In function 'mpc8xxx_spi_write_reg':
      drivers/spi/spi_fsl_lib.h:88:2: error: implicit declaration of function 'out_be32'
      drivers/spi/spi_fsl_lib.h: In function 'mpc8xxx_spi_read_reg':
      drivers/spi/spi_fsl_lib.h:93:2: error: implicit declaration of function 'in_be32'
      drivers/spi/spi_fsl_espi.c: In function 'fsl_espi_remove':
      drivers/spi/spi_fsl_espi.c:571:2: error: implicit declaration of function 'iounmap'
      drivers/spi/spi_fsl_espi.c: In function 'fsl_espi_probe':
      drivers/spi/spi_fsl_espi.c:602:2: error: implicit declaration of function 'ioremap'
      drivers/spi/spi_fsl_espi.c:602:24: warning: assignment makes pointer from integer without a cast
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      ef6510ba
  2. 13 10月, 2010 2 次提交
    • M
      spi/fsl_spi: add eSPI controller support · 8b60d6c2
      Mingkai Hu 提交于
      Add eSPI controller support based on the library code spi_fsl_lib.c.
      
      The eSPI controller is newer controller 85xx/Pxxx devices supported.
      There're some differences comparing to the SPI controller:
      
      1. Has different register map and different bit definition
         So leave the code operated the register to the driver code, not
         the common code.
      
      2. Support 4 dedicated chip selects
         The software can't controll the chip selects directly, The SPCOM[CS]
         field is used to select which chip selects is used, and the
         SPCOM[TRANLEN] field is set to tell the controller how long the CS
         signal need to be asserted. So the driver doesn't need the chipselect
         related function when transfering data, just set corresponding register
         fields to controll the chipseclect.
      
      3. Different Transmit/Receive FIFO access register behavior
         For SPI controller, the Tx/Rx FIFO access register can hold only
         one character regardless of the character length, but for eSPI
         controller, the register can hold 4 or 2 characters according to
         the character lengths. Access the Tx/Rx FIFO access register of the
         eSPI controller will shift out/in 4/2 characters one time. For SPI
         subsystem, the command and data are put into different transfers, so
         we need to combine all the transfers to one transfer in order to pass
         the transfer to eSPI controller.
      
      4. The max transaction length limitation
         The max transaction length one time is limitted by the SPCOM[TRANSLEN]
         field which is 0xFFFF. When used mkfs.ext2 command to create ext2
         filesystem on the flash, the read length will exceed the max value of
         the SPCOM[TRANSLEN] field.
      Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      8b60d6c2
    • M
      spi/mpc8xxx: refactor the common code for SPI/eSPI controller · b36ece83
      Mingkai Hu 提交于
      Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
      by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
      controller code in the SPI controller driver spi_fsl_spi.c.
      
      Because the register map of the SPI controller and eSPI controller
      is so different, also leave the code operated the register to the
      driver code, not the common code.
      Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      b36ece83