- 17 8月, 2014 3 次提交
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由 Florian Fainelli 提交于
BCM7xxx internal Gigabit PHY on 28nm process do not need anything special to be done during suspend, remove the suspend callback since it might be harmful rather than useful. While at it, update the comment above bcm7xxx_suspend() to reflect that it applies only to 40nm and 65nm process PHY devices. Fixes: b560a58c ("net: phy: add Broadcom BCM7xxx internal PHY driver") Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@greenl8ke.davemloft.net>
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由 Florian Fainelli 提交于
The BCM7xxx internal Gigabit PHYs on 28nm process platforms come out reset without any half-duplex or "hub" compatible advertised modes, which was causing auto-negotiation issues coming out of S3 suspend/resume, we just could not establish a link with a half-duplex only link partner. Make sure that the resume function properly re-configures the PHY device to advertise all supported modes. Fixes: b560a58c ("net: phy: add Broadcom BCM7xxx internal PHY driver") Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@greenl8ke.davemloft.net>
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由 Florian Fainelli 提交于
A wildcard entry with the 32-bits OUI 0x600d8400 was added as part of the BCM7xxx internal PHY driver, but that entry might match other PHYs that are not covered by this driver, so let's just remove it. Fixes: b560a58c ("net: phy: add Broadcom BCM7xxx internal PHY driver") Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@greenl8ke.davemloft.net>
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- 27 3月, 2014 3 次提交
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由 Florian Fainelli 提交于
The AFE_RX_LP_COUNTER kept the last 3 bits set, which would not properly clear the EEE LPI mode errors bits. Make sure that those bits are set to 0 to ensure the PHY timing is always good even during EEE wake-up. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Florian Fainelli 提交于
Writing first to the AFE registers, and then the VCO, RCAL, RC_CAL registers turned out to unveil some spurious MDIO read/write failures which would make the workaround partially applied. The fix is to write first to the VCO, RCAL, RC_CAL registers, and then write to the AFE registers. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Florian Fainelli 提交于
Define constants for the various registers used in bcm7xxx_28nm_afe_config_init() to help clarify what this workaround is about. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 2月, 2014 1 次提交
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由 Florian Fainelli 提交于
This patch adds support for the Broadcom BCM7xxx Set Top Box SoCs internal PHYs. This driver supports the following generation of SoCs: - BCM7366, BCM7439, BCM7445 (28nm process) - all 40nm and 65nm (older MIPS-based SoCs) The PHYs on these SoCs require a bunch of workarounds to operate correctly, both during configuration time and at suspend/resume time, the driver handles that for us. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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