1. 31 1月, 2009 1 次提交
  2. 29 1月, 2009 1 次提交
    • N
      [ARM] 5366/1: fix shared memory coherency with VIVT L1 + L2 caches · 08e445bd
      Nicolas Pitre 提交于
      When there are multiple L1-aliasing userland mappings of the same physical
      page, we currently remap each of them uncached, to prevent VIVT cache
      aliasing issues. (E.g. writes to one of the mappings not being immediately
      visible via another mapping.)  However, when we do this remapping, there
      could still be stale data in the L2 cache, and an uncached mapping might
      bypass L2 and go straight to RAM.  This would cause reads from such
      mappings to see old data (until the dirty L2 line is eventually evicted.)
      
      This issue is solved by forcing a L2 cache flush whenever the shared page
      is made L1 uncacheable.
      
      Ideally, we would make L1 uncacheable and L2 cacheable as L2 is PIPT. But
      Feroceon does not support that combination, and the TEX=5 C=0 B=0 encoding
      for XSc3 doesn't appear to work in practice.
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      08e445bd
  3. 28 1月, 2009 38 次提交