Taken from Realtek's 8.006.00 r8168 driver.

I have left some bits related to jumbo frame aside for now.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

Taken from Realtek's 8.006.00 r8168 driver.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

This part of the driver should be reasonably in line with Realtek's
8.006.00 driver.

I have left some bits related to jumbo frame and optional features
aside for now.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

Broadly speaking the 8168c* share some common code which will
be factored in __rtl_hw_start_8168cp. The 8168b* share some
code too but it will be a bit different.

Any change of behavior should be confined to the currently
unidentified 8168 chipsets. They will not be applied the Tx
performance tweak and will emit a warning instead.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

I can not argue strongly for (or against) a specific ordering
on a purely technical ground but the patch avoids to swallow
Realtek's changes in one big, hard-to-read gulp.

Let aside the way the RxConfig register is written (see
rtl_set_rx_tx_config_registers / RxConfig / rtl_set_rx_mode),
this change brings the registers write ordering closer with
Realtek's driver one (version 8.006.00) for the 8168 chipsets.

More 8168 specific code which touches the Configx registers will
be added in the section covered by Cfg9346_UnLock / Cfg9346_Lock.

This code should not be the cause of regression for 810x and
8110 users.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

The new parameters are synced with Realtek's driver
version 8.006.00.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

The modified parameters are synced with Realtek's driver
version 8.006.00.

The change should only be noticeable with some 8168c.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>

This is typically needed when some other OS puts the PHY
to sleep due to the disabling of WOL options in the BIOS
of the system.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Tested-by: NChiaki Ishikawa <chiaki.ishikawa@ubin.jp>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>
Cc: RyanKao <ryankao@realtek.com.tw>

rtl8169_init_one
-> rtl_init_mac_address
   -> rtl_rar_set
      -> spin_lock_irq(&tp->lock);
[...]
-> spin_lock_init(&tp->lock);
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Fix warnings caught by David Miller on sparc64
Signed-off-by: NSteve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The T5 timer is the timer for the over-all shutdown procedure.  If
this timer expires, then shutdown procedure has not completed and we
ABORT the association.  We should update SCTP_MIB_ABORTED and
SCTP_MIB_CURRESTAB  when aborting.
Signed-off-by: NVlad Yasevich <vladislav.yasevich@hp.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

If ABORT chunks require authentication and a protocol violation
is triggered, we do not tear down the association.  Subsequently,
we should not increment SCTP_MIB_ABORTED.
Signed-off-by: NVlad Yasevich <vladislav.yasevich@hp.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

RFC3873 defined SCTP_MIB_CURRESTAB:
  sctpCurrEstab OBJECT-TYPE
    SYNTAX         Gauge32
    MAX-ACCESS     read-only
    STATUS         current
    DESCRIPTION
         "The number of associations for which the current state is
         either ESTABLISHED, SHUTDOWN-RECEIVED or SHUTDOWN-PENDING."
    REFERENCE
         "Section 4 in RFC2960 covers the SCTP   Association state
         diagram."

If the T4 RTO timer expires many times(timeout), the association will enter
CLOSED state, so we should dec the number of SCTP_MIB_CURRESTAB, not inc the
number of SCTP_MIB_CURRESTAB.
Signed-off-by: NWei Yongjun <yjwei@cn.fujitsu.com>
Signed-off-by: NVlad Yasevich <vladislav.yasevich@hp.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

No need to modulus the queue number in ->hard_start_xmit() since the
core is going to do that for you modulus ->real_num_tx_queues.
Signed-off-by: NBrice Goglin <brice@myri.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When offloading transmit checksums only, the driver was not
correctly configuring the hardware to handle the case of a zero
checksum.  For UDP the correct behavior is to leave it alone, but
for tcp the checksum must be changed from 0x0000 to 0xFFFF.  The
hardware takes care of this case but only if it is told the
packet is tcp.

same patch as e1000e
Signed-off-by: NDave Graham <david.graham@intel.com>
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

When offloading transmit checksums only, the driver was not
correctly configuring the hardware to handle the case of a zero
checksum.  For UDP the correct behavior is to leave it alone, but
for tcp the checksum must be changed from 0x0000 to 0xFFFF.  The
hardware takes care of this case but only if it is told the
packet is tcp.
Signed-off-by: NDave Graham <david.graham@intel.com>
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Before, the driver would not care about the return codes from pci_map_*
functions.  This could be potentially dangerous if a mapping failed.
Now, we will check all pci_map_* calls.  On the transmit side, we switch
to use the new function skb_dma_map().  On the receive side, we add
pci_dma_mapping_error().
Signed-off-by: NBenjamin Li <benli@broadcom.com>
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This is now possible with updated firmware.
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

With this new firmware, the driver no longer has to modify the
TCP/IP header fields when transmitting TSO packets.
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

We need to check netif_running() state in most ethtool operations
and properly handle the !netif_running() state where the chip is
in an uninitailzed state or low power state that may not accept
any MMIO.
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NBenjamin Li <benli@broadcom.com>
Signed-off-by: NMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This logic is used in bnx2_close() and bnx2_suspend() and
so should be separated out into a separate function.
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NBenjamin Li <benli@broadcom.com>
Signed-off-by: NMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch makes the RX/TX byte counters for IPIP, GRE and SIT more
consistent.  Previously we included the external IP headers on the
way out but not when the packet is inbound.

The new scheme is to count payload only in both directions.  For
IPIP and SIT this simply means the exclusion of the external IP
header.  For GRE this means that we exclude the GRE header as
well.
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds support for Ethernet over GRE encapsulation.
This is exposed to user-space with a new link type of "gretap"
instead of "gre".  It will create an ARPHRD_ETHER device in
lieu of the usual ARPHRD_IPGRE.

Note that to preserver backwards compatibility all Transparent
Ethernet Bridging packets are passed to an ARPHRD_IPGRE tunnel
if its key matches and there is no ARPHRD_ETHER device whose
key matches more closely.
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds a netlink interface that will eventually displace
the existing ioctl interface.  It utilises the elegant rtnl_link_ops
mechanism.

This also means that user-space no longer needs to rely on the
tunnel interface being of type GRE to identify GRE tunnels.  The
identification can now occur using rtnl_link_ops.
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch moves the dev->mtu setting out of ipgre_tunnel_bind_dev.
This is in prepartion of using rtnl_link where we'll need to make
the MTU setting conditional on whether the user has supplied an
MTU.  This also requires the move of the ipgre_tunnel_bind_dev
call out of the dev->init function so that we can access the user
parameters later.

This patch also adds a check to prevent setting the MTU below
the minimum of 68.
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Now that we have dev->needed_headroom, we can use it instead of
having a bogus dev->hard_header_len.  This also allows us to
include dev->hard_header_len in the MTU computation so that when
we do have a meaningful hard_harder_len in future it is included
automatically in figuring out the MTU.

Incidentally, this fixes a bug where we ignored the needed_headroom
field of the underlying device in calculating our own hard_header_len.
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

1. arch/powerpc/platforms/pasemi/gpio_mdio.c also needs to be
   converted over to mdiobus_{alloc,free}().

2. drivers/net/phy/fixed.c used to embed a struct mii_bus into its
   struct fixed_mdio_bus and then use container_of() to go from the
   former to the latter.  Since mii bus structures are no longer
   embedded, we need to do something like use the mii bus private
   pointer to go from mii_bus to fixed_mdio_bus instead.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

drivers/net/jme.c:1598: warning: ‘jme_set_100m_half’ defined but not used
drivers/net/jme.c:1618: warning: ‘jme_wait_link’ defined but not used
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Advances the driver version after modification.
Signed-off-by: NGuo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Fix IRQ handle bug when interrupt mode.

The driver was incorrectly handled and returned IRQ_HANDLED
while the device is not generating the interrupt.
It happened due to faulty determination of interrupt status register.

Found by: "Ethan" <ethanhsiao@jmicron.com>
Fixed by: "akeemting" <akeem@jmicron.com>
Signed-off-by: NGuo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex
   mode. Which the MAC processor generates CRS/COL by itself instead of
   receive it from PHY processor.

2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the
   MAC processor working right while calculating IPv6 RSS in 10/100
   mode.

3. Group the workaround codes all together.
Signed-off-by: NGuo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add support for 1G optical Vitesse PHY.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add support for SR PHY.
Auto-detect phy module type, and report type changes.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add generic code to manage interrupt driven PHYs.
Do not reset the phy after link parameters update,
the new values might get lost.
Return early from link change notification
when the link parameters remain unchanged.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Do not require PHY interrupts to be connected to GPIs in ascending order.
Base interrupt availability both on PHYs supporting them and on GPIs being
hooked up.  Allows boards to specify interrupt GPIs though the PHYs don't
use them.

Remove spurious PHY interrupts due to clearing T3DBG interrupts before
setting their polarity.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Second step in overall phy layer reorganization.
Clean up the port_type_info structure.
Support coextistence of clause 22 and clause 45 MDIO devices.
Select the type of MDIO transaction on a per transaction basis.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

First step towards overall PHY layering re-organization.
Allow a status return when a PHY is reset.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Allocate a queue set per core, up to the maximum of available qsets.
Share the queue sets on multi port adapters.
Rename MSI-X interrupt vectors ethX-N, N being the queue set number.
Signed-off-by: NDivy Le Ray <divy@chelsio.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>