Zynq is standard PMU with 2 interrupt per core.
There is also access via register which is not used right now.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.

Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support for specifying clock information for the uart clk via the
device tree. This eliminates the need to hardcode rates in the device
tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add support for retrieving TTC configuration from device tree.  This
includes the ability to pull information about the driving clocks from
the of_clk bindings.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Make the Zynq platform use the newly created zynq clk bindings.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The purpose of the created zynq-7000.dtsi file is to describe the
hardware common to all Zynq 7000-based boards.  Also, get rid of the
zynq-ep107 device tree, since it is not hardware anyone can purchase.

Add a zc702 dts file based on the zynq-7000.dtsi.  Add it to the
dts/Makefile so it is built with the 'dtbs' target.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The zynq-7000 has an additional UART at 0xE0001000.  Describe it in the
device tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq has a PL310 L2 cache controller.  Convert in-tree uses to using
the device tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq uses the cortex-a9-gic.  This eliminates the need to hardcode
register addresses.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The 1st board support is minimal to get a system up and running
on the Xilinx platform.

This platform reuses the clock implementation from plat-versatile, and
it depends entirely on CONFIG_OF support.  There is only one board
support file which obtains all device information from a device tree
dtb file which is passed to the kernel at boot time.
Signed-off-by: NJohn Linn <john.linn@xilinx.com>