Merge tag 'clk-hisi-for-v3.16' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilicon

enable hix5hd2 clock

__clk_get_hw is supposed to be used by clk providers, not clk consumers.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

clk mvebu changes for v3.16

 - orion5x: brand new driver

Add MSTP clock support for the r8a7779 SoC

The only change required appears to be to note a new
compatibility string in the bindings.

Cc: devicetree@vger.kernel.org
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks are all fixed rate clocks with multiplier and
divisor set according to boot mode configuration.

Based on work for R-Car Gen2 SoCs by Laurent Pinchart.

Cc: devicetree@vger.kernel.org
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga

Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden.

Improve the wording for the clock-indices binding documentation.
Also replace "empty nodes" by "empty strings", as reported before by Sergei
Shtylyov.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

General:
  - Add parameter names to .round_rate() and .set_rate().

Documentation/clk.txt:
  - Add missing parameter for .set_rate(),
  - Add missing .debug_init().

include/linux/clk-provider.h:
  - Add parent rate documentation for .round_rate(),
  - Reorder documentation to match implementation order,
  - Add missing documentation for .init().
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

- Remove spaces in front of TABs,
- Correct indentation for some CLK_* flag descriptions.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

With the addition of clock-indices, we need to change the renesas
clock implementation to use these instead of the local definition
of "renesas,clock-indices".

Since this will break booting with older device trees, we add a
simple auto-detection of which properties are present.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.

This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Signed-off-by: NHaifeng Yan <haifeng.yan@linaro.org>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>

Add hisi_clk_register_gate register clk gate table
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>

Platform hix5hd2 use mux table, so use clk_register_mux_table instead
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>

HdG: add header exporting clk_sunxi_mmc_phase_control
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

* Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs
* Fix incorrect offset for PMIC_SSBI2_RESET
* Fix typo:
	SIC_TIC -> SPS_TIC_H
	SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK
* Fix naming convention:
	SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK
	SATA_SRC_CLK -> SATA_CLK_SRC
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The APQ8064 and MSM8960 share a significant amount of clock data and
code between the two SoCs.  Rather than duplicating the data we just add
support for a unqiue APQ8064 clock table into the MSM8960 code.

For now add just enough clocks to get a basic serial port going on an
APQ8064 device.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: trivial conflict due to missing ipq8064 support]

Most of the probe code is the same between all the different
clock controllers. Consolidate the code into a common.c file.
This makes changes to the common probe parts easier and reduces
chances for bugs.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This simplifies error paths in drivers that use optional clocks
by allowing the NULL or error pointer to be passed
unconditionally.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The same if-else statement exists four times to recalculate the
rate of a clock. Consolidate this logic into a single function to
save some lines.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

We dereference clk->ops during clock registration so this check
for NULL ops can't possibly ever be true.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Replace the "fake" fixed-rate clocks used previously for the
bcm21664 family with "real" ones.
Signed-off-by: NAlex Elder <elder@linaro.org>
Acked-by: NMatt Porter <mporter@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Define the set of CCUs and provided clocks sufficient to satisfy the
needs of all the existing clock references for BCM21664.  Replace
the "fake" fixed-rate clocks used previously with "real" ones.

Note that only the minimal set of these clocks and CCUs is defined
here.  More clock definitions will need to be added as required by
the addition of additional drivers.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Document the device tree binding for Broadcom BCM28164 clock control
units and clocks.  This SoC uses Kona CCUs, similar to the BCM281XX
SoC family.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The next patch defines a binding for a new Broadcom SoC that uses
Kona style CCUs for its clocks.  Update the generic Kona clock
binding document so it's more natural to accomodate the definitions
of additional SoC families.

Specifically:
    - Define the compatible string values generically, referring
      to specific per-model values later in the document.
    - Put the device tree example immediately after the required
      properties listing, before the tables of SoC-specific values.
    - Clearly identify the start of the section defining specific
      values related to the BCM281XX family
    - Add a list of the specific BCM281XX family compatible strings.
    - Reword the description of the table slightly.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The Broadcom 281xx clock code uses a #define for the compatible
string for it's clock control units (CCUs).  Rather than defining
those in the C source file, define them in the header file that's
shared by both the code and the device tree source file (along with
all the clock ids).
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add support for clock gate hysteresis control.  For now, if it's
defined for a clock, it's enabled.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add support for CCU policy engine control, and also for setting the
mask bits for bus clocks that require a policy change to get
activated.  This includes adding validity checking framework for
CCUs, to validate the policy fields if defined.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Rather than "manually" setting up each CCU's clock entries at run
time, define a flexible array of generic Kona clock structures
within the CCU structure itself.  Each of these entries contains
generic kona clock information (like its CCU pointer and clock
framework initialization data).  Each also has a pointer to a
structure contianing clock type-dependent initialization data
(like register definitions).

Since we'll iterate over these arrays we need to be sure they have
slots for all potential clock index values.  (E.g. for the root CCU
we must have at least BCM281XX_ROOT_CCU_CLOCK_COUNT slots.)  To
ensure this we always define an extra entry and fill it using the
special initializer LAST_KONA_CLK.

Just about everything we need to know about a clock can be defined
statically.  As a result, kona_clk_setup() can be changed to take
just a kona_clk structure as its argument, and peri_clk_setup() can
be simplified.  With the information pre-defined we are also able
to handle most clock setup genericially.  We can do away with the
CCU-specific callback functions that previously were needed to set
up the entries in CCU's clock array.

Move the definition of the ccu_data structure down in "clk-kona.h"
to avoid a forward dependency.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

We know up front how many CCU's we'll support, so there's no need to
allocate their data structures dynamically.  Define a macro
KONA_CCU_COMMON() to simplify the initialization of many of the
fields in a ccu_data structure.  Pass the address of a statically
defined CCU structure to kona_dt_ccu_setup() rather than having that
function allocate one.

We also know at build time how many clocks a given CCU will provide,
though the number of of them for each CCU is different.  Record the
number of clocks we need in the CCU's clk_onecell_data struct
(which is used when we register the CCU with the common clock code
as a clock provider).  Rename that struct field "clk_data" (because
"data" alone gets a little confusing).

Use the known clock count to move the allocation of each CCU's
clocks array into ccu_clks_setup() rather than having each CCU's
setup callback function do it.

(The real motivation behind all of this is that we'll be doing some
static initialization of some additional CCU-specific data soon.)
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

As I developed the bcm281xx clock code I understood there were
restrictions on device tree "compatible" strings names, and as a
result "bcm11351" was used in places despite the part family being
more properly called "bcm281xx".  This can be a little confusing.

In some cases I went to far and things using "bcm11351" when that
was not necessary.

This patch remedies this.  It renames the symbol used to define the
"compatible" string (but not its value) so it uses "BCM281XX".
Similarly, the name names provided to the CLK_OF_DECLARE() macro
are changed, hoping to minimize the number of places that the
confusing "11351" string is used.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Use the init_data.name field to hold the name of a Kona clock rather
than duplicating it.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Don't let a failure of ccu_wait_bit() go unnoticed.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Currently, the for-loop used to try all the different dividers to find the
one that best fit tries all the values from 1 to max_div, incrementing by one.
In case of power-of-two, or table based divider, the loop isn't optimal.

Instead of incrementing by one, this patch provides directly the next divider.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

In some cases, we want to be able to round the divider to the closest one,
instead than rounding up.

This patch adds a new CLK_DIVIDER_ROUND_CLOSEST flag to specify the divider
has to round to closest div, keeping rounding up as de default behaviour.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

When a clock is unregsitered, we iterate over the list of
children and reparent them to NULL (i.e. orphan list). While
iterating the list, we should use the safe iterators because the
children list for this clock is changing when we reparent the
children to NULL. Failure to iterate safely can lead to slab
corruption like this:

=============================================================================
BUG kmalloc-128 (Not tainted): Poison overwritten
-----------------------------------------------------------------------------

Disabling lock debugging due to kernel taint
INFO: 0xed0c4900-0xed0c4903. First byte 0x0 instead of 0x6b
INFO: Allocated in clk_register+0x20/0x1bc age=297 cpu=2 pid=70
 __slab_alloc.isra.39.constprop.42+0x410/0x454
 kmem_cache_alloc_trace+0x200/0x24c
 clk_register+0x20/0x1bc
 devm_clk_register+0x34/0x68
 0xbf0000f0
 platform_drv_probe+0x18/0x48
 driver_probe_device+0x94/0x360
 __driver_attach+0x94/0x98
 bus_for_each_dev+0x54/0x88
 bus_add_driver+0xe8/0x204
 driver_register+0x78/0xf4
 do_one_initcall+0xc4/0x17c
 load_module+0x19ac/0x2294
 SyS_init_module+0xa4/0x110
 ret_fast_syscall+0x0/0x48
INFO: Freed in clk_unregister+0xd4/0x140 age=23 cpu=2 pid=73
 __slab_free+0x38/0x41c
 clk_unregister+0xd4/0x140
 release_nodes+0x164/0x1d8
 __device_release_driver+0x60/0xb0
 driver_detach+0xb4/0xb8
 bus_remove_driver+0x5c/0xc4
 SyS_delete_module+0x148/0x1d8
 ret_fast_syscall+0x0/0x48
INFO: Slab 0xeec50b90 objects=25 used=0 fp=0xed0c5400 flags=0x4080
INFO: Object 0xed0c48c0 @offset=2240 fp=0xed0c4a00

Bytes b4 ed0c48b0: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a  ZZZZZZZZZZZZZZZZ
Object ed0c48c0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
Object ed0c48d0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
Object ed0c48e0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
Object ed0c48f0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
Object ed0c4900: 00 00 00 00 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  ....kkkkkkkkkkkk
Object ed0c4910: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
Object ed0c4920: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
Object ed0c4930: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5  kkkkkkkkkkkkkkk.
Redzone ed0c4940: bb bb bb bb                                      ....
Padding ed0c49e8: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a  ZZZZZZZZZZZZZZZZ
Padding ed0c49f8: 5a 5a 5a 5a 5a 5a 5a 5a                          ZZZZZZZZ
CPU: 3 PID: 75 Comm: mdev Tainted: G    B         3.14.0-11033-g2054ba5ca781 #35
[<c0014be0>] (unwind_backtrace) from [<c0012240>] (show_stack+0x10/0x14)
[<c0012240>] (show_stack) from [<c04b74a0>] (dump_stack+0x70/0xbc)
[<c04b74a0>] (dump_stack) from [<c00f7a78>] (check_bytes_and_report+0xbc/0x100)
[<c00f7a78>] (check_bytes_and_report) from [<c00f7c48>] (check_object+0x18c/0x218)
[<c00f7c48>] (check_object) from [<c00f7efc>] (__free_slab+0x104/0x144)
[<c00f7efc>] (__free_slab) from [<c04b6668>] (__slab_free+0x3dc/0x41c)
[<c04b6668>] (__slab_free) from [<c014c008>] (load_elf_binary+0x88/0x12b4)
[<c014c008>] (load_elf_binary) from [<c0105a44>] (search_binary_handler+0x78/0x18c)
[<c0105a44>] (search_binary_handler) from [<c0106fc0>] (do_execve+0x490/0x5dc)
[<c0106fc0>] (do_execve) from [<c0036b8c>] (____call_usermodehelper+0x134/0x168)
[<c0036b8c>] (____call_usermodehelper) from [<c000f048>] (ret_from_fork+0x14/0x2c)
FIX kmalloc-128: Restoring 0xed0c4900-0xed0c4903=0x6b

Fixes: fcb0ee6a (clk: Implement clk_unregister)
Cc: Jiada Wang <jiada_wang@mentor.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: stable@vger.kernel.org

Now that clk_unregister() frees the struct clk we're
unregistering we'll free memory twice: first we'll call kfree()
in __clk_release() with an address kmalloc doesn't know about and
second we'll call kfree() in the devres layer. Remove the
allocation of struct clk in devm_clk_register() and let
clk_release() handle it. This fixes slab errors like:

=============================================================================
BUG kmalloc-128 (Not tainted): Invalid object pointer 0xed08e8d0
-----------------------------------------------------------------------------

Disabling lock debugging due to kernel taint
INFO: Slab 0xeec503f8 objects=25 used=15 fp=0xed08ea00 flags=0x4081
CPU: 2 PID: 73 Comm: rmmod Tainted: G    B         3.14.0-11032-g526e9c764381 #34
[<c0014be0>] (unwind_backtrace) from [<c0012240>] (show_stack+0x10/0x14)
[<c0012240>] (show_stack) from [<c04b74dc>] (dump_stack+0x70/0xbc)
[<c04b74dc>] (dump_stack) from [<c00f6778>] (slab_err+0x74/0x84)
[<c00f6778>] (slab_err) from [<c04b6278>] (free_debug_processing+0x2cc/0x31c)
[<c04b6278>] (free_debug_processing) from [<c04b6300>] (__slab_free+0x38/0x41c)
[<c04b6300>] (__slab_free) from [<c03931bc>] (clk_unregister+0xd4/0x140)
[<c03931bc>] (clk_unregister) from [<c02fb774>] (release_nodes+0x164/0x1d8)
[<c02fb774>] (release_nodes) from [<c02f8698>] (__device_release_driver+0x60/0xb0)
[<c02f8698>] (__device_release_driver) from [<c02f9080>] (driver_detach+0xb4/0xb8)
[<c02f9080>] (driver_detach) from [<c02f8480>] (bus_remove_driver+0x5c/0xc4)
[<c02f8480>] (bus_remove_driver) from [<c008c9b8>] (SyS_delete_module+0x148/0x1d8)
[<c008c9b8>] (SyS_delete_module) from [<c000ef80>] (ret_fast_syscall+0x0/0x48)
FIX kmalloc-128: Object at 0xed08e8d0 not freed

Fixes: fcb0ee6a (clk: Implement clk_unregister)
Cc: Jiada Wang <jiada_wang@mentor.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: stable@vger.kernel.org

Merge tag 'socfpga-clk-fix-for-3.15' of git://git.rocketboards.org/linux-socfpga-next into clk-fixes-socfpga

clk: socfpga: clock fix for v3.15

Currently on 3.15-rc1, the SOCFPGA platform is unable to boot. This patch
fixes the issue and allows the platform to boot.