1. 30 5月, 2014 5 次提交
    • J
      MIPS: KVM: Quieten kvm_info() logging · 6e95bfd2
      James Hogan 提交于
      The logging from MIPS KVM is fairly noisy with kvm_info() in places
      where it shouldn't be, such as on VM creation and migration to a
      different CPU. Replace these kvm_info() calls with kvm_debug().
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      6e95bfd2
    • J
      MIPS: KVM: Remove ifdef DEBUG around kvm_debug · d5c704d5
      James Hogan 提交于
      kvm_debug() uses pr_debug() which is already compiled out in the absence
      of a DEBUG define, so remove the unnecessary ifdef DEBUG lines around
      kvm_debug() calls which are littered around arch/mips/kvm/.
      
      As well as generally cleaning up, this prevents future bit-rot due to
      DEBUG not being commonly used.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      d5c704d5
    • J
      MIPS: KVM: Fix kvm_debug bit-rottage · 3d654833
      James Hogan 提交于
      Fix build errors when DEBUG is defined in arch/mips/kvm/.
       - The DEBUG code in kvm_mips_handle_tlbmod() was missing some variables.
       - The DEBUG code in kvm_mips_host_tlb_write() was conditional on an
         undefined "debug" variable.
       - The DEBUG code in kvm_mips_host_tlb_inv() accessed asid_map directly
         rather than using kvm_mips_get_user_asid(). Also fixed brace
         placement.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      3d654833
    • J
      MIPS: KVM: Migrate hrtimer to follow VCPU · 3a0ba774
      James Hogan 提交于
      When a VCPU is scheduled in on a different CPU, refresh the hrtimer used
      for emulating count/compare so that it gets migrated to the same CPU.
      
      This should prevent a timer interrupt occurring on a different CPU to
      where the guest it relates to is running, which would cause the guest
      timer interrupt not to be delivered until after the next guest exit.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      3a0ba774
    • J
      MIPS: KVM: Use tlb_write_random · b5dfc6c1
      James Hogan 提交于
      When MIPS KVM needs to write a TLB entry for the guest it reads the
      CP0_Random register, uses it to generate the CP_Index, and writes the
      TLB entry using the TLBWI instruction (tlb_write_indexed()).
      
      However there's an instruction for that, TLBWR (tlb_write_random()) so
      use that instead.
      
      This happens to also fix an issue with Ingenic XBurst cores where the
      same TLB entry is replaced each time preventing forward progress on
      stores due to alternating between TLB load misses for the instruction
      fetch and TLB store misses.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      b5dfc6c1
  2. 25 1月, 2014 3 次提交
    • P
      mips: delete non-required instances of include <linux/init.h> · 3b2663ca
      Paul Gortmaker 提交于
      None of these files are actually using any __init type directives
      and hence don't need to include <linux/init.h>.  Most are just a
      left over from __devinit and __cpuinit removal, or simply due to
      code getting copied from one driver to the next.
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: NJohn Crispin <blogic@openwrt.org>
      Patchwork: http://patchwork.linux-mips.org/patch/6320/
      3b2663ca
    • J
      MIPS: KVM: remove shadow_tlb code · 08596b0a
      James Hogan 提交于
      The kvm_mips_init_shadow_tlb() function is called from
      kvm_arch_vcpu_init() and initialises entries 0 to
      current_cpu_data.tlbsize-1 of the virtual cpu's shadow_tlb[64] array.
      
      However newer cores with FTLBs can have a tlbsize > 64, for example the
      ProAptiv I'm testing on has a total tlbsize of 576. This causes
      kvm_mips_init_shadow_tlb() to overflow the shadow_tlb[64] array and
      overwrite the comparecount_timer among other things, causing a lock up
      when starting a KVM guest.
      
      Aside from kvm_mips_init_shadow_tlb() which only initialises it, the
      shadow_tlb[64] array is only actually used by the following functions:
       - kvm_shadow_tlb_put() & kvm_shadow_tlb_load()
           These are never called. The only call sites are #if 0'd out.
       - kvm_mips_dump_shadow_tlbs()
           This is never called.
      
      It was originally added for trap & emulate, but turned out to be
      unnecessary so it was disabled.
      
      So instead of fixing the shadow_tlb initialisation code, lets just
      remove the shadow_tlb[64] array and the above functions entirely. The
      only functional change here is the removal of broken shadow_tlb
      initialisation. The rest just deletes dead code.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Gleb Natapov <gleb@redhat.com>
      Cc: kvm@vger.kernel.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NJohn Crispin <blogic@openwrt.org>
      Patchwork: http://patchwork.linux-mips.org/patch/6384/
      08596b0a
    • J
      MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI · e36059e5
      James Hogan 提交于
      When KVM is enabled and TLB invalidation is supported,
      kvm_mips_flush_host_tlb() can cause a machine check exception due to
      multiple matching TLB entries. This can occur on shutdown even when KVM
      hasn't been actively used.
      
      Commit adb78de9eae8 (MIPS: mm: Move UNIQUE_ENTRYHI macro to a header
      file) created a common UNIQUE_ENTRYHI in asm/tlb.h but it didn't update
      the copy of UNIQUE_ENTRYHI in kvm_tlb.c to use it.
      
      Commit 36b175451399 (MIPS: tlb: Set the EHINV bit for TLBINVF cores when
      invalidating the TLB) later added TLB invalidation (EHINV) support to
      the common UNIQUE_ENTRYHI.
      
      Therefore make kvm_tlb.c use the EHINV aware UNIQUE_ENTRYHI
      implementation in asm/tlb.h too.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: Gleb Natapov <gleb@redhat.com>
      Cc: kvm@vger.kernel.org
      Cc: Sanjay Lal <sanjayl@kymasys.com>
      Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com>
      Acked-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NJohn Crispin <blogic@openwrt.org>
      Patchwork: http://patchwork.linux-mips.org/patch/6383/
      e36059e5
  3. 22 5月, 2013 1 次提交
  4. 17 5月, 2013 1 次提交
  5. 08 5月, 2013 1 次提交
    • S
      KVM/MIPS32: MMU/TLB operations for the Guest. · 858dd5d4
      Sanjay Lal 提交于
      - Note that this file is statically linked with the rest of the host kernel (KSEG0). This is because kernel modules are
      loaded into mapped space on MIPS and we want to make sure that we don't get any host kernel TLB faults while
      manipulating TLBs.
      - Virtual Guest TLBs are implemented as 64 entry array regardless of the number of host TLB entries.
      - Shadow TLBs map Guest virtual addresses to Host physical addresses.
      
          - TLB miss handling details:
              Guest KSEG0 TLBMISS (0x40000000 – 0x60000000): Transparent to the Guest.
              Guest KSEG2/3 (0x60000000 – 0x80000000) & Guest UM TLBMISS (0x00000000 – 0x40000000)
                  Lookup in Guest/Virtual TLB
                  If an entry doesn’t match
                      deliver appropriate TLBMISS LD/ST exception to the guest
                  If entry does exist in the Guest TLB and is NOT Valid
                      Deliver TLB invalid exception to the guest
                  If entry does exist in the Guest TLB and is VALID
                      Inject the TLB entry into the Shadow TLB
      Signed-off-by: NSanjay Lal <sanjayl@kymasys.com>
      Cc: kvm@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      858dd5d4