提交 · 6e0ad1b6c1c9809a8ea9ca647cbc0471e8b4164d · openanolis / cloud-kernel

17 1月, 2014 6 次提交

clk: qcom: Add support for branches/gate clocks · 6e0ad1b6

由 Stephen Boyd 提交于 1月 15, 2014

Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

6e0ad1b6

clk: qcom: Add support for root clock generators (RCGs) · bcd61c0f

由 Stephen Boyd 提交于 1月 15, 2014

Add support for the root clock generators on Qualcomm devices.
RCGs are highly customizable mux/divider/counter clocks that can
be used to generate almost any rate desired given some input
source that is faster than the desired rate.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

bcd61c0f

clk: qcom: Add support for phase locked loops (PLLs) · 9e263131

由 Stephen Boyd 提交于 1月 15, 2014

Add support for Qualcomm's PLLs (phase locked loops). This is
sufficient enough to be able to determine the rate the PLL is
running at. We can add rate setting support later when it's
needed.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

9e263131

clk: qcom: Add a regmap type clock struct · 085d7a45

由 Stephen Boyd 提交于 1月 15, 2014

Add a clock type that associates a regmap pointer and some
enable/disable bits with a clk_hw struct. This will be the struct
that a hw specific implementation wraps if it wants to use the
regmap helper functions.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

085d7a45

clk: Add set_rate_and_parent() op · 3fa2252b

由 Stephen Boyd 提交于 1月 15, 2014

Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

3fa2252b

clk: sirf: re-arch to make the codes support both prima2 and atlas6 · 7bf21bc8

由 Barry Song 提交于 1月 15, 2014

sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for
prima2 and atlas6, there are many shared clocks but there are still
some different register layout and hardware clocks, then result in
different clock table.

here we re-arch the driver to
1. clk-common.c provides common clocks for prima2 and atlas6,
2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides
prima2 specific clocks and clock table.
3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides
atlas6 specific clocks and clock table.
4. clk.h and clk.c expose external interfaces and provide uniform entry
for both prima2 and atlas6.

so both prima2 and atlas6 will get support by drivers/clk/sirf.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NRongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

7bf21bc8

15 1月, 2014 3 次提交

clk: composite: pass mux_hw into determine_rate · 5d2043fb

由 Mike Turquette 提交于 1月 14, 2014

The composite clock's .determine_rate implementation can call the
underyling .determine_rate callback corresponding to rate_hw or the
underlying .determine_rate callback corresponding to mux_hw. In both
cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into
the correct callback.
Reported-by: NLemon Dai <dailemon.gl@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

5d2043fb

clk: shmobile: Fix MSTP clock array initialization · 209f4fed

由 Valentine Barshak 提交于 12月 28, 2013

The clks member of the clk_onecell_data structure should
point to a valid clk array (no NULL entries allowed),
and the clk_num should be equal to the number
of elements in the clks array.

The MSTP driver fails to satisfy the above conditions.
The clks array may contain NULL entries if not all
clock-indices are initialized in the device tree.
Thus, if the clock indices are interleaved we end up
with NULL pointers in-between.

The other problem is the driver uses maximum clock index
as the number of clocks, which is incorrect (less than
the actual number of clocks by 1).

Fix the first issue by pre-setting the whole clks array
with ERR_PTR(-ENOENT) pointers instead of zeros; and
use maximum clkidx + 1 as the number of clocks to fix
the other one.

This should make of_clk_src_onecell_get() return the following:
* valid clk pointers for all clocks registered;
* ERR_PTR(-EINVAL) if (idx >= clk_data->clk_num);
* ERR_PTR(-ENOENT) if the clock at the selected index was not
  initialized in the device tree (and was not registered).

Changes in V2:
* removed brackets from the one-line for loop
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

209f4fed

clk: shmobile: Fix MSTP clock index · 6413b090

由 Valentine Barshak 提交于 12月 28, 2013

Use clkidx when registering MSTP clocks instead of loop counter
since the value is then used to access the specific clock index bit
in the mstp register.

The issue was introduced by the following commit:
f94859c2 "clk: shmobile: Add MSTP clock support"

Changes in V2:
* none
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

6413b090

09 1月, 2014 16 次提交

clk: max77686: Register OF clock provider · b06c6987