1. 12 10月, 2019 1 次提交
  2. 12 8月, 2018 1 次提交
  3. 12 7月, 2018 2 次提交
    • M
      arm64: kill config_sctlr_el1() · 25be597a
      Mark Rutland 提交于
      Now that we have sysreg_clear_set(), we can consistently use this
      instead of config_sctlr_el1().
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reviewed-by: NDave Martin <dave.martin@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Cc: James Morse <james.morse@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      25be597a
    • M
      arm64: move SCTLR_EL{1,2} assertions to <asm/sysreg.h> · 1c312e84
      Mark Rutland 提交于
      Currently we assert that the SCTLR_EL{1,2}_{SET,CLEAR} bits are
      self-consistent with an assertion in config_sctlr_el1(). This is a bit
      unusual, since config_sctlr_el1() doesn't make use of these definitions,
      and is far away from the definitions themselves.
      
      We can use the CPP #error directive to have equivalent assertions in
      <asm/sysreg.h>, next to the definitions of the set/clear bits, which is
      a bit clearer and simpler.
      
      At the same time, lets fill in the upper 32 bits for both registers in
      their respective RES0 definitions. This could be a little nicer with
      GENMASK_ULL(63, 32), but this currently lives in <linux/bitops.h>, which
      cannot safely be included from assembly, as <asm/sysreg.h> can.
      
      Note the when the preprocessor evaluates an expression for an #if
      directive, all signed or unsigned values are treated as intmax_t or
      uintmax_t respectively. To avoid ambiguity, we define explicitly define
      the mask of all 64 bits.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Cc: Dave Martin <dave.martin@arm.com>
      Cc: James Morse <james.morse@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      1c312e84
  4. 09 7月, 2018 1 次提交
  5. 21 6月, 2018 1 次提交
    • M
      arm64: Introduce sysreg_clear_set() · 6ebdf4db
      Mark Rutland 提交于
      Currently we have a couple of helpers to manipulate bits in particular
      sysregs:
      
       * config_sctlr_el1(u32 clear, u32 set)
      
       * change_cpacr(u64 val, u64 mask)
      
      The parameters of these differ in naming convention, order, and size,
      which is unfortunate. They also differ slightly in behaviour, as
      change_cpacr() skips the sysreg write if the bits are unchanged, which
      is a useful optimization when sysreg writes are expensive.
      
      Before we gain yet another sysreg manipulation function, let's
      unify these with a common helper, providing a consistent order for
      clear/set operands, and the write skipping behaviour from
      change_cpacr(). Code will be migrated to the new helper in subsequent
      patches.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reviewed-by: NDave Martin <dave.martin@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      6ebdf4db
  6. 20 3月, 2018 1 次提交
    • S
      arm64: Expose Arm v8.4 features · 7206dc93
      Suzuki K Poulose 提交于
      Expose the new features introduced by Arm v8.4 extensions to
      Arm v8-A profile.
      
      These include :
      
       1) Data indpendent timing of instructions. (DIT, exposed as HWCAP_DIT)
       2) Unaligned atomic instructions and Single-copy atomicity of loads
          and stores. (AT, expose as HWCAP_USCAT)
       3) LDAPR and STLR instructions with immediate offsets (extension to
          LRCPC, exposed as HWCAP_ILRCPC)
       4) Flag manipulation instructions (TS, exposed as HWCAP_FLAGM).
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Reviewed-by: NDave Martin <dave.martin@arm.com>
      Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      7206dc93
  7. 26 2月, 2018 1 次提交
    • M
      arm64/kvm: Prohibit guest LOR accesses · cc33c4e2
      Mark Rutland 提交于
      We don't currently limit guest accesses to the LOR registers, which we
      neither virtualize nor context-switch. As such, guests are provided with
      unusable information/controls, and are not isolated from each other (or
      the host).
      
      To prevent these issues, we can trap register accesses and present the
      illusion LORegions are unssupported by the CPU. To do this, we mask
      ID_AA64MMFR1.LO, and set HCR_EL2.TLOR to trap accesses to the following
      registers:
      
      * LORC_EL1
      * LOREA_EL1
      * LORID_EL1
      * LORN_EL1
      * LORSA_EL1
      
      ... when trapped, we inject an UNDEFINED exception to EL1, simulating
      their non-existence.
      
      As noted in D7.2.67, when no LORegions are implemented, LoadLOAcquire
      and StoreLORelease must behave as LoadAcquire and StoreRelease
      respectively. We can ensure this by clearing LORC_EL1.EN when a CPU's
      EL2 is first initialized, as the host kernel will not modify this.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Vladimir Murzin <vladimir.murzin@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: kvmarm@lists.cs.columbia.edu
      Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org>
      cc33c4e2
  8. 16 1月, 2018 7 次提交
  9. 09 1月, 2018 2 次提交
  10. 05 1月, 2018 1 次提交
  11. 23 12月, 2017 1 次提交
  12. 03 11月, 2017 2 次提交
    • D
      arm64/sve: System register and exception syndrome definitions · 67236564
      Dave Martin 提交于
      The SVE architecture adds some system registers, ID register fields
      and a dedicated ESR exception class.
      
      This patch adds the appropriate definitions that will be needed by
      the kernel.
      Signed-off-by: NDave Martin <Dave.Martin@arm.com>
      Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      67236564
    • D
      arm64: KVM: Hide unsupported AArch64 CPU features from guests · 93390c0a
      Dave Martin 提交于
      Currently, a guest kernel sees the true CPU feature registers
      (ID_*_EL1) when it reads them using MRS instructions.  This means
      that the guest may observe features that are present in the
      hardware but the host doesn't understand or doesn't provide support
      for.  A guest may legimitately try to use such a feature as per the
      architecture, but use of the feature may trap instead of working
      normally, triggering undef injection into the guest.
      
      This is not a problem for the host, but the guest may go wrong when
      running on newer hardware than the host knows about.
      
      This patch hides from guest VMs any AArch64-specific CPU features
      that the host doesn't support, by exposing to the guest the
      sanitised versions of the registers computed by the cpufeatures
      framework, instead of the true hardware registers.  To achieve
      this, HCR_EL2.TID3 is now set for AArch64 guests, and emulation
      code is added to KVM to report the sanitised versions of the
      affected registers in response to MRS and register reads from
      userspace.
      
      The affected registers are removed from invariant_sys_regs[] (since
      the invariant_sys_regs handling is no longer quite correct for
      them) and added to sys_reg_desgs[], with appropriate access(),
      get_user() and set_user() methods.  No runtime vcpu storage is
      allocated for the registers: instead, they are read on demand from
      the cpufeatures framework.  This may need modification in the
      future if there is a need for userspace to customise the features
      visible to the guest.
      
      Attempts by userspace to write the registers are handled similarly
      to the current invariant_sys_regs handling: writes are permitted,
      but only if they don't attempt to change the value.  This is
      sufficient to support VM snapshot/restore from userspace.
      
      Because of the additional registers, restoring a VM on an older
      kernel may not work unless userspace knows how to handle the extra
      VM registers exposed to the KVM user ABI by this patch.
      
      Under the principle of least damage, this patch makes no attempt to
      handle any of the other registers currently in
      invariant_sys_regs[], or to emulate registers for AArch32: however,
      these could be handled in a similar way in future, as necessary.
      Signed-off-by: NDave Martin <Dave.Martin@arm.com>
      Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      93390c0a
  13. 18 10月, 2017 1 次提交
  14. 11 10月, 2017 1 次提交
    • S
      arm64: Expose support for optional ARMv8-A features · f5e035f8
      Suzuki K Poulose 提交于
      ARMv8-A adds a few optional features for ARMv8.2 and ARMv8.3.
      Expose them to the userspace via HWCAPs and mrs emulation.
      
      SHA2-512  - Instruction support for SHA512 Hash algorithm (e.g SHA512H,
      	    SHA512H2, SHA512U0, SHA512SU1)
      SHA3 	  - SHA3 crypto instructions (EOR3, RAX1, XAR, BCAX).
      SM3	  - Instruction support for Chinese cryptography algorithm SM3
      SM4 	  - Instruction support for Chinese cryptography algorithm SM4
      DP	  - Dot Product instructions (UDOT, SDOT).
      
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Dave Martin <dave.martin@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f5e035f8
  15. 09 8月, 2017 1 次提交
  16. 26 7月, 2017 1 次提交
  17. 23 6月, 2017 1 次提交
  18. 15 6月, 2017 8 次提交
  19. 07 6月, 2017 1 次提交
  20. 21 3月, 2017 3 次提交
  21. 10 3月, 2017 2 次提交
    • M
      arm64: sysreg: add Set/Way sys encodings · 4dc52925
      Mark Rutland 提交于
      Cache maintenance ops fall in the SYS instruction class, and KVM needs
      to handle them. So as to keep all SYS encodings in one place, this
      patch adds them to sysreg.h.
      
      The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-2.
      
      To make it clear that these are instructions rather than registers, and
      to allow us to change the way these are handled in future, a new
      sys_insn() alias for sys_reg() is added and used for these new
      definitions.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      4dc52925
    • M
      arm64: sysreg: add register encodings used by KVM · 14ae7518
      Mark Rutland 提交于
      This patch adds sysreg definitions for registers which KVM needs the
      encodings for, which are not currently describe in <asm/sysregs.h>.
      Subsequent patches will make use of these definitions.
      
      The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-6, but
      this is not an exhaustive addition. Additions are only made for
      registers used today by KVM.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      14ae7518