1. 10 4月, 2015 1 次提交
  2. 11 2月, 2015 1 次提交
  3. 24 9月, 2014 1 次提交
    • B
      ARM: mm: Fix ifdef around cpu_*_do_[suspend, resume] ops · f6f1ae82
      Bartlomiej Zolnierkiewicz 提交于
      Ifdef around cpu_\name\()_do_suspend and cpu_\name\()_do_resume
      ops in proc-macros.S should check for CONFIG_ARM_CPU_SUSPEND and
      not CONFIG_PM_SLEEP.  Fix it.
      
      [ Please note that cpu_v7_do_[suspend,resume] code in proc-v7.S
        already correctly checks for CONFIG_ARM_CPU_SUSPEND, same is
        true for functions for other architectures. ]
      
      This fix is needed for decoupling suspend/resume and advanced
      cpuidle support on Exynos platform (next patch fixes build for
      config with CONFIG_PM_SLEEP=n and CONFIG_ARM_EXYNOS_CPUIDLE=y).
      
      If this fix is not present then the following OOPS happens on
      the first attempt to go into advanced cpuidle mode (AFTR):
      
      [   22.244143] Unable to handle kernel NULL pointer dereference at virtual address 00000000
      [   22.250759] pgd = c0004000
      [   22.253445] [00000000] *pgd=00000000
      [   22.257012] Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
      [   22.262906] Modules linked in:
      [   22.265949] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.16.0-next-20140811-dirty #730
      [   22.273757] task: c05dce68 ti: c05d2000 task.ti: c05d2000
      [   22.279139] PC is at 0x0
      [   22.281661] LR is at __cpu_suspend_save+0x4c/0xa8
      [   22.286344] pc : [<00000000>]    lr : [<c00125e0>]    psr: a0000093
      [   22.286344] sp : c05d3ef4  ip : c05da414  fp : 00000001
      [   22.297799] r10: c05da414  r9 : c0609cb0  r8 : 0000000f
      [   22.303008] r7 : c05da444  r6 : 00000038  r5 : ea802c00  r4 : c05d3f14
      [   22.309517] r3 : 00000000  r2 : c05d3f4c  r1 : 00000038  r0 : c05d3f20
      [   22.316029] Flags: NzCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
      [   22.323406] Control: 10c5387d  Table: 69d5404a  DAC: 00000015
      [   22.329135] Process swapper/0 (pid: 0, stack limit = 0xc05d2240)
      [   22.335124] Stack: (0xc05d3ef4 to 0xc05d4000)
      [   22.339466] 3ee0:                                              ea802c00 00000038 c05d3f4c
      [   22.347626] 3f00: 00000000 00000007 c00123bc 00000000 c001d468 6a888000 c05d3f4c 80000000
      [   22.355785] 3f20: 00000007 c003d3a0 0000193d eaf9dde4 eaf9dde4 c02ef0c8 c000969c fffffffe
      [   22.363944] 3f40: 00000000 c0037b54 eaf9dbb8 e9d1a380 00000000 c001d468 c0609cb0 00000000
      [   22.372103] 3f60: c0609cb0 c061649e 00000001 c001250c eaf9dbb8 00000001 c0609cb0 c001d618
      [   22.380262] 3f80: c001d5d0 c02ef56c 2d9d2e1e 00000005 eaf9dbb8 c02edcc4 2d9d2e1e 00000005
      [   22.388421] 3fa0: c040446c c05da4ec c040446c eaf9dbb8 c05cfbb0 c004c580 c05dce68 c05b3ae8
      [   22.396580] 3fc0: 00000000 c058bb24 ffffffff ffffffff c058b5e4 00000000 00000000 c05b3ae8
      [   22.404740] 3fe0: c0616994 c05da47c c05b3ae4 c05ddeec 4000406a 40008074 00000000 00000000
      [   22.412909] [<c00125e0>] (__cpu_suspend_save) from [<c00123bc>] (__cpu_suspend+0x5c/0x70)
      [   22.421074] [<c00123bc>] (__cpu_suspend) from [<c05d3f4c>] (init_thread_union+0x1f4c/0x2000)
      [   22.429479] Code: bad PC value
      [   22.432518] ---[ end trace fb90ebf4217d0ad9 ]---
      [   22.437116] Kernel panic - not syncing: Attempted to kill the idle task!
      [   22.443800] Rebooting in 5 seconds..
      
      This patch has been tested on Exynos4210 based Origen board.
      Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
      Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      f6f1ae82
  4. 10 2月, 2014 1 次提交
    • W
      ARM: 7954/1: mm: remove remaining domain support from ARMv6 · b6ccb980
      Will Deacon 提交于
      CPU_32v6 currently selects CPU_USE_DOMAINS if CPU_V6 and MMU. This is
      because ARM 1136 r0pX CPUs lack the v6k extensions, and therefore do
      not have hardware thread registers. The lack of these registers requires
      the kernel to update the vectors page at each context switch in order to
      write a new TLS pointer. This write must be done via the userspace
      mapping, since aliasing caches can lead to expensive flushing when using
      kmap. Finally, this requires the vectors page to be mapped r/w for
      kernel and r/o for user, which has implications for things like put_user
      which must trigger CoW appropriately when targetting user pages.
      
      The upshot of all this is that a v6/v7 kernel makes use of domains to
      segregate kernel and user memory accesses. This has the nasty
      side-effect of making device mappings executable, which has been
      observed to cause subtle bugs on recent cores (e.g. Cortex-A15
      performing a speculative instruction fetch from the GIC and acking an
      interrupt in the process).
      
      This patch solves this problem by removing the remaining domain support
      from ARMv6. A new memory type is added specifically for the vectors page
      which allows that page (and only that page) to be mapped as user r/o,
      kernel r/w. All other user r/o pages are mapped also as kernel r/o.
      Patch co-developed with Russell King.
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      b6ccb980
  5. 24 6月, 2013 1 次提交
    • G
      ARM: 7773/1: PJ4B: Add support for errata 4742 · 3e0a07f8
      Gregory CLEMENT 提交于
      This commit fixes the regression on Armada 370 (the kernal hang during
      boot) introduced by the commit: "ARM: 7691/1: mm: kill unused
      TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead".
      
      When coming out of either a Wait for Interrupt (WFI) or a Wait for
      Event (WFE) IDLE states, a specific timing sensitivity exists between
      the retiring WFI/WFE instructions and the newly issued subsequent
      instructions. This sensitivity can result in a CPU hang scenario.  The
      workaround is to insert either a Data Synchronization Barrier (DSB) or
      Data Memory Barrier (DMB) command immediately after the WFI/WFE
      instruction.
      
      This commit was based on the work of Lior Amsalem, but heavily
      modified to apply the errata fix dynamically according to the
      processor type thanks to the suggestions of Russell King and Nicolas
      Pitre.
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Reviewed-by: NWill Deacon <will.deacon@arm.com>
      Acked-by: NNicolas Pitre <nico@linaro.org>
      Tested-by: NWilly Tarreau <w@1wt.eu>
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      3e0a07f8
  6. 17 2月, 2013 1 次提交
  7. 09 11月, 2012 1 次提交
    • W
      ARM: mm: introduce present, faulting entries for PAGE_NONE · 26ffd0d4
      Will Deacon 提交于
      PROT_NONE mappings apply the page protection attributes defined by _P000
      which translate to PAGE_NONE for ARM. These attributes specify an XN,
      RDONLY pte that is inaccessible to userspace. However, on kernels
      configured without support for domains, such a pte *is* accessible to
      the kernel and can be read via get_user, allowing tasks to read
      PROT_NONE pages via syscalls such as read/write over a pipe.
      
      This patch introduces a new software pte flag, L_PTE_NONE, that is set
      to identify faulting, present entries.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      26ffd0d4
  8. 25 9月, 2012 1 次提交
    • L
      ARM: mm: implement LoUIS API for cache maintenance ops · 031bd879
      Lorenzo Pieralisi 提交于
      ARM v7 architecture introduced the concept of cache levels and related
      control registers. New processors like A7 and A15 embed an L2 unified cache
      controller that becomes part of the cache level hierarchy. Some operations in
      the kernel like cpu_suspend and __cpu_disable do not require a flush of the
      entire cache hierarchy to DRAM but just the cache levels belonging to the
      Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
      correspond to L1.
      
      The current cache flushing API used in cpu_suspend and __cpu_disable,
      flush_cache_all(), ends up flushing the whole cache hierarchy since for
      v7 it cleans and invalidates all cache levels up to Level of Coherency
      (LoC) which cripples system performance when used in hot paths like hotplug
      and cpuidle.
      
      Therefore a new kernel cache maintenance API must be added to cope with
      latest ARM system requirements.
      
      This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.
      
      This function cleans and invalidates all data cache levels up to the
      Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
      cache for processors that support it (> v7).
      
      This patch also creates an alias of the cache LoUIS function to flush_kern_all
      for all processor versions prior to v7, so that the current cache flushing
      behaviour is unchanged for those processors.
      
      v7 cache maintenance code implements a cache LoUIS function that cleans and
      invalidates the D-cache up to LoUIS and invalidates the I-cache, according
      to the new API.
      Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Reviewed-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Tested-by: NShawn Guo <shawn.guo@linaro.org>
      031bd879
  9. 08 12月, 2011 1 次提交
    • C
      ARM: LPAE: MMU setup for the 3-level page table format · 1b6ba46b
      Catalin Marinas 提交于
      This patch adds the MMU initialisation for the LPAE page table format.
      The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new
      proc-v7-3level.S file contains the TTB initialisation, context switch
      and PTE setting code with the LPAE. The TTBRx split is based on the
      PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings
      (supersections) and a few other memory types in mmu.c are conditionally
      compiled.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      1b6ba46b
  10. 22 7月, 2011 1 次提交
  11. 07 7月, 2011 1 次提交
  12. 31 3月, 2011 1 次提交
  13. 22 12月, 2010 3 次提交
  14. 13 12月, 2010 2 次提交
  15. 04 11月, 2010 1 次提交
    • C
      ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUs · 247055aa
      Catalin Marinas 提交于
      This patch removes the domain switching functionality via the set_fs and
      __switch_to functions on cores that have a TLS register.
      
      Currently, the ioremap and vmalloc areas share the same level 1 page
      tables and therefore have the same domain (DOMAIN_KERNEL). When the
      kernel domain is modified from Client to Manager (via the __set_fs or in
      the __switch_to function), the XN (eXecute Never) bit is overridden and
      newer CPUs can speculatively prefetch the ioremap'ed memory.
      
      Linux performs the kernel domain switching to allow user-specific
      functions (copy_to/from_user, get/put_user etc.) to access kernel
      memory. In order for these functions to work with the kernel domain set
      to Client, the patch modifies the LDRT/STRT and related instructions to
      the LDR/STR ones.
      
      The user pages access rights are also modified for kernel read-only
      access rather than read/write so that the copy-on-write mechanism still
      works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register
      (CPU_32v6K is defined) since writing the TLS value to the high vectors page
      isn't possible.
      
      The user addresses passed to the kernel are checked by the access_ok()
      function so that they do not point to the kernel space.
      Tested-by: NAnton Vorontsov <cbouatmailru@gmail.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      247055aa
  16. 24 7月, 2009 1 次提交
  17. 11 7月, 2009 1 次提交
  18. 01 10月, 2008 3 次提交
  19. 09 5月, 2007 1 次提交
  20. 29 6月, 2006 1 次提交
    • R
      [ARM] nommu: provide a way for correct control register value selection · 22b19086
      Russell King 提交于
      Most MMU-based CPUs have a restriction on the setting of the data cache
      enable and mmu enable bits in the control register, whereby if the data
      cache is enabled, the MMU must also be enabled.  Enabling the data
      cache without the MMU is an invalid combination.
      
      However, there are CPUs where the data cache can be enabled without the
      MMU.
      
      In order to allow these CPUs to take advantage of that, provide a
      method whereby each proc-*.S file defines the control regsiter value
      for use with nommu (with the MMU disabled.)  Later on, when we add
      support for enabling the MMU on these devices, we can adjust the
      "crval" macro to also enable the data cache for nommu.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      22b19086
  21. 10 9月, 2005 1 次提交
  22. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4