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  1. 25 3月, 2011 1 次提交
  3. 24 2月, 2011 1 次提交
  5. 04 2月, 2011 5 次提交
    • R
      ARM: mmci: add dmaengine-based DMA support · c8ebae37
      由 Russell King 提交于 
      Based on a patch from Linus Walleij.

Add dmaengine based support for DMA to the MMCI driver, using the
Primecell DMA engine interface.  The changes over Linus' driver are:

- rename txsize_threshold to dmasize_threshold, as this reflects the
  purpose more.
- use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'.
- clean up requesting of dma channels.
- don't release a single channel twice when it's shared between tx and rx.
- get rid of 'dma_enable' bool - instead check whether the channel is NULL.
- detect incomplete DMA at the end of a transfer.  Some DMA controllers
  (eg, PL08x) are unable to be configured for scatter DMA and also listen
  to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI.
  They can do one or other but not both.  As MMCI uses LBREQ/LSREQ for the
  final burst/words, PL08x does not transfer the last few words.
- map and unmap DMA buffers using the DMA engine struct device, not the
  MMCI struct device - the DMA engine is doing the DMA transfer, not us.
- avoid double-unmapping of the DMA buffers on MMCI data errors.
- don't check for negative values from the dmaengine tx submission
  function - Dan says this must never fail.
- use new dmaengine helper functions rather than using the ugly function
  pointers directly.
- allow DMA code to be fully optimized away using dma_inprogress() which
  is defined to constant 0 if DMA engine support is disabled.
- request maximum segment size from the DMA engine struct device and
  set this appropriately.
- removed checking of buffer alignment - the DMA engine should deal with
  its own restrictions on buffer alignment, not the individual DMA engine
  users.
- removed setting DMAREQCTL - this confuses some DMA controllers as it
  causes LBREQ to be asserted for the last seven transfers, rather than
  six SREQ and one LSREQ.
- removed burst setting - the DMA controller should not burst past the
  transfer size required to complete the DMA operation.
Tested-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c8ebae37
    • R
      ARM: mmci: no need for separate host->data_xfered · 51d4375d
      由 Russell King 提交于 
      We don't need to store the number of bytes transferred in our host
structure - we can store this directly in data->bytes_xfered.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      51d4375d
    • R
      ARM: mmci: avoid unnecessary switch to data available PIO interrupts · c4d877c1
      由 Russell King 提交于 
      We don't need to switch to data available interrupts if there's at
least half a FIFO depth worth of data remaining, as we'll still get
the FIFO half full interrupt.  Keep this interrupt masked off until
we have less than half the FIFO depth worth of data remaining.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c4d877c1
    • R
      ARM: mmci: no need to call flush_dcache_page() with sg_miter API · 7d7aa23c
      由 Russell King 提交于 
      The sg_miter API provides the required cache maintainence, so we don't
need to do that ourselves.  Remove the unnecessary additional cache
maintainence.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7d7aa23c
    • R
      ARM: mmci: avoid reporting too many completed bytes on fifo overrun · c8afc9d5
      由 Russell King 提交于 
      The data counter counts the number of bytes transferred on the MMC bus.
When a FIFO overrun occurs, we will not have transferred a FIFOs-worth
of data to memory, and so the data counter will be a FIFOs-worth ahead.
If this occurs on a block boundary, we will report one too many sectors
as successful.  Fix this.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      c8afc9d5
  7. 31 1月, 2011 2 次提交
  9. 28 1月, 2011 1 次提交
  11. 26 1月, 2011 1 次提交
  13. 24 1月, 2011 1 次提交
  15. 30 12月, 2010 1 次提交
  17. 20 12月, 2010 2 次提交
  19. 10 11月, 2010 3 次提交
  21. 23 10月, 2010 2 次提交
  23. 23 9月, 2010 3 次提交
  25. 27 8月, 2010 2 次提交
  27. 31 7月, 2010 1 次提交
  29. 29 7月, 2010 4 次提交
  31. 27 7月, 2010 3 次提交
  33. 28 5月, 2010 1 次提交
  35. 14 4月, 2010 2 次提交
  37. 22 2月, 2010 1 次提交
  39. 28 1月, 2010 1 次提交
  41. 24 11月, 2009 1 次提交
  43. 01 10月, 2009 1 次提交