The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

chips have some issues for version and capbility registers, here we fake
them.
Signed-off-by: NWeijun Yang <Weijun.Yang@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

hardware has 16bit to record the tuning count, so fix it to 16384.
at the same time, tuned_phases[SIRF_TUNING_COUNT] is useless as the
array is never used, so move it to a variant.
Signed-off-by: NWeijun Yang <Weijun.Yang@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Clean up resource allocation and freeing.
Signed-off-by: NIan Molton <ian.molton@codethink.co.uk>
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Signed-off-by: NIan Molton <ian.molton@codethink.co.uk>
[bwh: Forward-ported to 4.0]
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Signed-off-by: NIan Molton <ian.molton@codethink.co.uk>
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhci_alloc_host() takes priv_size rather than
sizeof(struct sdhci_host) + priv_size.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Make local functions static.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

For PowerPC esdhc pre divider starts at 1, fixing the increases
the actual clock from 40KHz to 50 KHz.
Signed-off-by: NJoakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

My Pengutronix address is not valid anymore, redirect people to the Pengutronix
kernel team.
Reported-by: NHarald Geyer <harald@ccbib.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NRobert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Current sh_mmcif_clk_update() is called from probe() and set_ios(),
but, the purpose of later one is just clk_prepare_enable().
No need to setup mmc->f_max/f_min in many times.
This patch separe sh_mmcif_clk_update() into clk_prepare_enable()
and mmc->f_max/f_min setup.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

struct sh_mmcif_host has 1) int clk, 2) struct clock *hclk,
and host->clk = clk_get_rate(host->hclk).
This int clk is not necessary. Let's remove it.
And, current hclk is confusable naming. Let's rename it to clk.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

clkdiv is declared as an u32 but it can be set to a negative value
causing a huge divisor value. Change its type to int to avoid this case.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Cc: <stable@vger.kernel.org> # 3.4 and later
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

When non-removable is used for emmc,  MMC_CAP_NONREMOVABLE should
also be checked, otherwise detection fail since present=0
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Set 0 to des1 in 32bit case.
Otherwise the random value of des1 will be used in
dw_mci_translate_sglist: IDMAC_SET_BUFFER1_SIZE(desc, length)
Signed-off-by: NFei Wang <w.f@huawei.com>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

f9fd54f2 ("mmc: sh_mmcif: Use msecs_to_jiffies() for host->timeout")
changed the timeout value from 1000 jiffies to 1s. In the case where
HZ is 1000 the values are the same. However, for smaller HZ values the
timeout is now smaller, 1s instead of 10s in the case of HZ=100.

Since the timeout occurs in spite of a normal data transfer a timeout of
10s seems more appropriate. This restores the previous timeout in the
case where HZ=100 and results in an increase over the previous timeout
for larger values of HZ.

Fixes: f9fd54f2 ("mmc: sh_mmcif: Use msecs_to_jiffies() for host->timeout")
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[horms: rewrote changelog to refer to HZ]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Some additional quirks need to be enabled now we support UHS
modes. This avoids some spurious warnings like

"Got data interrupt 0x00000002 even though no data operation was in progress"

Testing on stih410-b2120 board achieves the following speeds
with HS200 eMMC card.

max-frequency = 200Mhz
/dev/mmcblk0p1:
 Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec

max-frequency = 100Mhz
root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec

max-frequency = 50Mhz
root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

This is better than the 3.10 kernel which achieves 77.59 MB/sec
at 200Mhz clock (same board/soc/eMMC).
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

To allow UHS modes to work properly we need to provide the st specific
set_uhs_signaling callback function. This function differs from the
generic sdhci_set_uhs_signaling callback in that we need to configure
the correct delay depending on the UHS mode, and also set the V18_EN
bit.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

STiH407 family SoC's have glue registers in the flashSS subsystem which
are used to configure the Arasan HC. This patch configures these glue
registers according to what has been specified in the DT.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Due to the tight timing constraints in some UHS modes, it is required to have
some delay management in the design. Two types of delay management are supported
in the HW: -

1) Static delay management
2) Dynamic delay management

NB: The delay management is only there when eMMC interface is selected.

1: Static delay management: is used to provide PVT dependent static delay on the
clock/data lines to manage setup/hold requirements of the interface. The maximum
delay possible is 3.25ns. These delays are PVT dependent, and thus delay values
applied are not accurate and vary across provcess voltage and temperature range.
Due to this these delays must not be used on the very time critical paths.

2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management.
The advantage of DLL is that it provides accurate & PVT indepedent delay.

The DLL is used to provide delay on the loopback clock on "Read Path" to capture
read data reliably. On TX path the clock on which output data is transmitted is
delayed, resulting in delay of TX data.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

STiH407 family SoC's can have a reset signal for the controller which needs to
be managed. Also the eMMC controller has some additional 'top' memory mapped
registers which are used to manage the dynamic and static delay required for
UHS modes. This patch adds support for creating the mapping, which will be used
by subsequent patches.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The stih407 family SoC's have additional glue registers in the flashSS which
are used to configure the Arasan controller.

This patch adds macros for the register offsets and bitfields which will be
used by subsequent patches to support stih407 family SoC's.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Currently it is not possible to use 'mmc-pwrseq-simple' property with this
driver because mmc_of_parse() is never called.

mmc_of_parse() calls mmc_pwrseq_alloc() that manages MMC power sequence and
allows passing GPIOs in the devicetree to properly power/reset the Wifi
chipset.

When using mmc_of_parse() we no longer need to have custom code to request
card-detect and write-protect pins, as this can now be handled by the mmc
core.

Tested on a imx6sl-warp board where BT/Wifi is functional and also on a
imx6q-sabresd.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

It is possible for the cmd11 interrupt to fire and delete the
cmd11_timer before the cmd11_timer was actually setup.  Let's fix this
race by adding a few spinlocks.  Note that the race wasn't seen in
practice without adding some printk statements, but it still seems
wise to fix.

Fixes: 5c935165 ("mmc: dw_mmc: Add a timeout for sending CMD11")
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

If we get an unexpected cmd11 timeout we shouldn't actually treat it
as a timeout (not that we really expect to get an unexpected cmd11
timeout, but still).

Fixes: 5c935165 ("mmc: dw_mmc: Add a timeout for sending CMD11")
Reported-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Although the cmd11 interrupt should come within 2ms, that's a very
short time.  Let's increase the timeout to be really sure that we
don't get an accidnetal timeout.  One case in particular this is
useful is if you've got a serial console and printk in just the right
places.  Under that scenario I've seen delays of up to 130ms before
the interrupt fired.

CMD11 is only sent during card insertion, so this extra timeout
shouldn't be terrible.

Fixes: 5c935165 ("mmc: dw_mmc: Add a timeout for sending CMD11")
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The dw_mmc driver changes to make the IO accesors endian agnostic did not
take into account the fifo accesses do not need to be swapped. To fix this
add a mmci_fifo_read/write wrapper to allow these to be passed through the
IO without being swapped.

Since these are now specific functions, it would be easier just to store
the pointer to the fifo registers in the host block instead of the offset
to them. So change the host->data_offset to host->fifo_reg (which also
means we catch all the places this is read or written).
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The dw_mmc driver does not take into account the processor may be in
big endian when writing the descriptors. Change the descriptors for
the 32bit IDMA to use __le32 and ensure they are suitably swapped
before writing.

Note, this has not been tested as the socfpga driver does not try to
use idma.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The dw_mmc driver does not use endian agnostic IO accessors, so fix
the use of __raw reads and writes to be the relaxed versions.

This fixes the dw_mmc driver initialisation on Altera socfpga in big endian.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Also check MMC OF properties. The controller supports MMC too.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

rts5250 chip failed handle 64 bit ADMA for address below 4G.
Add 64 BIT quirks to disable this feature.
Signed-off-by: NMicky Ching <micky_ching@realsil.com.cn>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Modify the driver to handle GPIOs using the descriptor API.
Signed-off-by: NMylene JOSSERAND <josserand.mylene@gmail.com>
Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com>
Tested-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Signed-off-by: NAndreas Fenkart <afenkart@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

strip the card dectet logic from cover detect isr and vice versa
the generic mmc_gpio_cd_irqt isr, uses 200ms on removal/insertion,
hence that should be fine here as well
Signed-off-by: NAndreas Fenkart <afenkart@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

If dw_mci_init_slot() returns that we got a probe deferral then it may
leave slot->mmc as NULL.  That will cause dw_mci_enable_cd() to crash
when it calls mmc_gpio_get_cd().

Fix this by moving the call of dw_mci_enable_cd() until we're sure
that we're good.  Note that if we have more than one slot and one
defers (but the others don't) things won't work so well.  ...but
that's not a new thing and everyone has already agreed that multislot
support ought to be removed from dw_mmc eventually anyway since it is
unused, untested, and you can see several bugs like this by inspecting
the code.

Fixes: bcafaf5470f0 ("mmc: dw_mmc: Only enable CD after setup and only if needed")
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>