1. 15 4月, 2014 1 次提交
  2. 26 3月, 2014 1 次提交
  3. 10 2月, 2014 1 次提交
  4. 03 2月, 2014 1 次提交
  5. 18 12月, 2013 6 次提交
  6. 15 11月, 2013 1 次提交
  7. 26 9月, 2013 1 次提交
  8. 29 8月, 2013 2 次提交
  9. 15 8月, 2013 1 次提交
    • J
      spi/spi-{bcm63xx.c,bfin-v3.c}: simplify use of devm_ioremap_resource · de0fa83c
      Julia Lawall 提交于
      Remove unneeded error handling on the result of a call to
      platform_get_resource when the value is passed to devm_ioremap_resource.
      
      Move the call to platform_get_resource adjacent to the call to
      devm_ioremap_resource to make the connection between them more clear.
      
      A simplified version of the semantic patch that makes this change is as
      follows: (http://coccinelle.lip6.fr/)
      
      // <smpl>
      @@
      expression pdev,res,n,e,e1;
      expression ret != 0;
      identifier l;
      @@
      
      - res = platform_get_resource(pdev, IORESOURCE_MEM, n);
        ... when != res
      - if (res == NULL) { ... \(goto l;\|return ret;\) }
        ... when != res
      + res = platform_get_resource(pdev, IORESOURCE_MEM, n);
        e = devm_ioremap_resource(e1, res);
      // </smpl>
      Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      de0fa83c
  10. 30 7月, 2013 1 次提交
  11. 30 5月, 2013 1 次提交
  12. 13 5月, 2013 1 次提交
  13. 08 4月, 2013 1 次提交
  14. 13 3月, 2013 12 次提交
  15. 06 2月, 2013 1 次提交
    • J
      spi/bcm63xx: work around inability to keep CS up · b17de076
      Jonas Gorski 提交于
      This SPI controller does not support keeping CS asserted after sending
      a transfer.
      Since messages expected on this SPI controller are rather short, we can
      work around it for normal use cases by sending all transfers at once in
      a big full duplex stream.
      
      This means that we cannot change the speed between transfers if they
      require CS to be kept asserted, but these would have been rejected
      before anyway because of the inability of keeping CS asserted.
      Signed-off-by: NJonas Gorski <jogo@openwrt.org>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      b17de076
  16. 05 2月, 2013 1 次提交
  17. 08 12月, 2012 1 次提交
  18. 17 10月, 2012 3 次提交
  19. 17 8月, 2012 1 次提交
    • F
      MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348. · 5a670445
      Florian Fainelli 提交于
      BCM6338 and BCM6348 have a message control register width of 8 bits, instead
      of 16-bits like what the SPI driver assumes right now. Also the SPI message
      type shift value of 14 is actually 6 for these SoCs.
      This resulted in transmit FIFO corruption because we were writing 16-bits
      to an 8-bits wide register, thus spanning on the first byte of the transmit
      FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().
      
      Fix this by passing the message control register width and message type
      shift through platform data back to the SPI driver so that it can use
      it properly.
      Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
      Cc: linux-mips@linux-mips.org
      Cc: grant.likely@secretlab.ca
      Cc: spi-devel-general@lists.sourceforge.net
      Cc: jonas.gorski@gmail.com
      Patchwork: https://patchwork.linux-mips.org/patch/3983/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5a670445
  20. 13 8月, 2012 1 次提交
  21. 23 7月, 2012 1 次提交