1. 22 5月, 2010 1 次提交
  2. 16 5月, 2010 1 次提交
    • S
      MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 · 95e8f634
      Shane McDonald 提交于
          
          In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
          are not currently writeable by the ctc1 instruction.  In odd corner cases,
          this can cause problems.  For example, a case existed where a divide-by-zero
          exception was generated by the FPU, and the signal handler attempted to
          restore the FPU registers to their state before the exception occurred.  In
          this particular setup, writing the old value to the FCSR register would
          cause another divide-by-zero exception to occur immediately.  The solution
          is to change the ctc1 instruction emulator code to allow the Cause bits of
          the FCSR register to be writeable.  This is the behaviour of the hardware
          that the code is emulating.
          
          This problem was found by Shane McDonald, but the credit for the fix goes
          to Kevin Kissell.  In Kevin's words:
          
          I submit that the bug is indeed in that ctc_op:  case of the emulator.  The
          Cause bits (17:12) are supposed to be writable by that instruction, but the
          CTC1 emulation won't let them be updated by the instruction.  I think that
          actually if you just completely removed lines 387-388 [...] things would
          work a good deal better.  At least, it would be a more accurate emulation of
          the architecturally defined FPU.  If I wanted to be really, really pedantic
          (which I sometimes do), I'd also protect the reserved bits that aren't
          necessarily writable.
      Signed-off-by: NShane McDonald <mcdonald.shane@gmail.com>
          To: anemo@mba.ocn.ne.jp
          To: kevink@paralogos.com
          To: sshtylyov@mvista.com
          Patchwork: http://patchwork.linux-mips.org/patch/1205/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      
      ---
      95e8f634
  3. 17 12月, 2009 1 次提交
    • D
      MIPS: Collect FPU emulator statistics per-CPU. · b6ee75ed
      David Daney 提交于
      On SMP systems, the collection of statistics can cause cache line
      bouncing in the lines associated with the counters.  Also there are
      races incrementing the counters on multiple CPUs.
      
      To fix both problems, we collect the statistics in per-CPU variables,
      and add them up in the debugfs read operation.
      
      As a test I ran the LTP float_bessel test on a 12 CPU Octeon system.
      
      Without CONFIG_DEBUG_FS :             2602 seconds.
      With CONFIG_DEBUG_FS:                 2640 seconds.
      With non-cpu-local atomic statistics: 14569 seconds.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      b6ee75ed
  4. 14 11月, 2009 1 次提交
    • D
      MIPS: Fix emulation of 64-bit FPU on FPU-less 64-bit CPUs. · da0bac33
      David Daney 提交于
      Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the
      emulator to run in 32-bit mode.  The c0_Status.FR bit is wired to zero
      on systems without an FPU, so using that bit to decide how the emulator
      behaves doesn't allow for proper emulation on 64-bit FPU-less
      processors.
      
      Instead, we need to select the emulator mode based on the user-space
      ABI.  Since the thread flag TIF_32BIT_REGS is used to set c0_Status.FR,
      we can just use it to decide if the emulator should be in 32-bit or
      64-bit mode.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      da0bac33
  5. 30 10月, 2008 1 次提交
  6. 28 10月, 2008 1 次提交
  7. 12 10月, 2007 2 次提交
  8. 14 7月, 2007 1 次提交
  9. 11 7月, 2007 1 次提交
  10. 10 10月, 2006 1 次提交
  11. 20 6月, 2006 1 次提交
  12. 30 10月, 2005 7 次提交
  13. 05 9月, 2005 1 次提交
    • Y
      [PATCH] mips: fix build warnings · 766160c2
      Yoichi Yuasa 提交于
      This patch has fixed the following warnings.
      
      arch/mips/kernel/genex.S:250:5: warning: "CONFIG_64BIT" is not defined
      arch/mips/math-emu/cp1emu.c:1128:5: warning: "__mips64" is not defined
      arch/mips/math-emu/cp1emu.c:1206:5: warning: "__mips64" is not defined
      arch/mips/math-emu/cp1emu.c:1270:5: warning: "__mips64" is not defined
      arch/mips/math-emu/cp1emu.c:323:5: warning: "__mips64" is not defined
      arch/mips/math-emu/cp1emu.c:808:5: warning: "__mips64" is not defined
      arch/mips/math-emu/cp1emu.c:953:5: warning: "__mips64" is not defined
      arch/mips/mm/tlbex.c:519:5: warning: "CONFIG_64BIT" is not defined
      include/asm/reg.h:73:5: warning: "CONFIG_64BIT" is not defined
      Signed-off-by: NYoichi Yuasa <yuasa@hh.iij4u.or.jp>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      766160c2
  14. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4