All the pieces were ready, just matter of assembling
them together.
Signed-off-by: NRiku Voipio <riku.voipio@iki.fi>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The RTC and the two XOR engines are internal to the chip, and therefore
always available since they don't depend on a particular board layout.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Signed-off-by: NNicolas Pitre <nico@marvell.com>

Signed-off-by: NNicolas Pitre <nico@marvell.com>

Signed-off-by: NNicolas Pitre <nico@marvell.com>

ts78xx add NAND support via plat_nand
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

amend RTC registering to not depend on ifdef's
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

Added checks to the platform_device_(register|add) calls so that if
a device failed to load it would then not later be unloaded; also
added the hooks so that it would not try to unload when the RTC
driver support is compiled out.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>
Signed-off-by: NNicolas Pitre <nico@cam.org>

The A0 revision of the mv78xx0 development board has four ethernet
ports, with PHY IDs 8-11, whereas the Z0 version has two, with PHY
addresses 8-9.  This patch configures the third and fourth ethernet
port to use the PHY addresses on the A0 board to enable use of those
ports -- if we are running on a Z0 board, the ge10/11 setup code in
common.c will force these back to PHYless mode.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

On pre-A0 revisions of the mv78xx0 SoC, the third and fourth
ethernet interface are not brought out to pins, but are internally
cross-connected, so if we run on pre-A0 silicon, we'll force eth2
and eth3 to PHYless mode.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

During boot, identify which chip stepping we're running on (determined
by looking at the first PCIe unit's device ID and revision registers),
and print a message with the details about what we found.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This allows for board support code to set up their MPP config if the
bootloader didn't do it all or did it wrong.  This also allows to
register usable GPIOs.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Especially on Kirkwood, a couple GPIOs are actually only output capable.
Let's separate the ability to configure a GPIO as input or output to
accommodate this restriction.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Remove the gesbc9312.h header since it is unused.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

READ_IMPLIES_EXEC must be set when:
o binary _is_ an executable stack (i.e. not EXSTACK_DISABLE_X)
o processor architecture is _under_ ARMv6 (XN bit is supported from ARMv6)
Signed-off-by: NMakito SHIOKAWA <lkhmkt@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When changing the parent of a clock, it is necessary to keep the
clock use counts balanced otherwise things the parent state will
get corrupted.  Since we already disable and re-enable the clock,
we might as well use the recursive versions instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In the non highmem case, if two memory banks of 1GB each are provided,
the second bank would evade suppression since its virtual base would
be 0.  Fix this by disallowing any memory bank which virtual base
address is found to be lower than PAGE_OFFSET.
Reported-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The GPIO interrupts can be configured as either level triggered or edge
triggered, with a default of level triggered.  When an edge triggered
interrupt is requested, the gpio_irq_set_type method is called which
currently switches the given IRQ descriptor between two struct irq_chip
instances: orion_gpio_irq_level_chip and orion_gpio_irq_edge_chip. This
happens via __setup_irq() which also calls irq_chip_set_defaults() to
assign default methods to uninitialized ones.  The problem is that
irq_chip_set_defaults() is called before the irq_chip reference is
switched, leaving the new irq_chip (orion_gpio_irq_edge_chip in this
case) with uninitialized methods such as chip->startup() causing a kernel
oops.

Many solutions are possible, such as making irq_chip_set_defaults() global
and calling it from gpio_irq_set_type(), or calling __irq_set_trigger()
before irq_chip_set_defaults() in __setup_irq().  But those require
modifications to the generic IRQ code which might have adverse effect on
other architectures, and that would still be a fragile arrangement.
Manually copying the missing methods from within gpio_irq_set_type()
would be really ugly and it would break again the day new methods with
automatic defaults are added.

A better solution is to have a single irq_chip instance which can deal
with both edge and level triggered interrupts.  It is also a good idea
to switch the IRQ handler instead, as the edge IRQ handler allows for
one edge IRQ event to be queued as the IRQ is actually masked only when
that second IRQ is received, at which point the hardware can queue an
additional IRQ event, making edge triggered interrupts a bit more
reliable.
Tested-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add support for inverted rdy_busy pin for Atmel nand device controller
It will fix building error on NeoCore926 board.
Acked-by: NAndrew Victor <linux@maxim.org.za>
Acked-by: NDavid Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: NGregory CLEMENT <gclement@adeneo.adetelgroup.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Enable the GPIO clocks earlier in the initialization sequence.  This
allow the board-setup code to read and set GPIO pins.
Signed-off-by: NMarc Pignat <marc.pignat@hevs.ch>
Signed-off-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The recently merged AT91SAM9 watchdog driver uses the
AT91SAM9X_WATCHDOG config variable, whereas the original version of
the driver (and the platform support code) used AT91SAM9_WATCHDOG.
This causes the watchdog platform_device to never be registered, and
therefore the driver not to be initialized.

This patch:
- updates the platform support code to use AT91SAM9X_WATCHDOG.
- includes <linux/io.h> to fix compile error (same fix as was applied
to at91rm9200_wdt.c)
- fixes comment regarding watchdog clock-rates in at91rm9200.
Signed-off-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

_omap2_clksel_get_src_field() was returning the first entry which was
either the default _or_ applicable to the SoC.  This is wrong - we
should be returning the first default which is applicable to the SoC.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The error checks for omap2_divisor_to_clksel() and comment disagree with
the actual value returned on error.  Fix this to return the correct error
value.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The C99 specification states in section 6.11.5:

The placement of a storage-class specifier other than at the beginning of the
declaration specifiers in a declaration is an obsolescent feature.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

the FPGA on the TS-7800 provides access to a number of devices
and so we have to be careful when reprogramming it.  As we
are effectively turning a bus off/on we have to inform the
kernel that it should stop using anything provided by the
FPGA (currently only the RTC however the NAND, LCD, etc is
to come) before it's reprogrammed.

Once reprogramed, we can tell the kernel to (re)enable things
by checking the FPGA ID against a lookup table for what a
particular FPGA bitstream can provide.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

moved the MPP comments to the mpp area of the platform code
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

The TS-7800's M25P40 is not available to the kernel, it's used
to load the initial bitstream onto the FPGA and so these hooks
point to nothing and need to be removed.
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

The TS-7800 can have a M48T86 RTC onboard
Signed-off-by: NAlexander Clouter <alex@digriz.org.uk>

This patch adds a MX2/MX3 specific SDHC driver. The hardware is basically
the same as in the MX1, but unlike the MX1 controller the MX2
controller just works as expected. Since the MX1 driver has more
workarounds for bugs than anything else I had no success with supporting
MX1 and MX2 in a sane way in one driver.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>

"flash" is a very generic name for a platform_driver that is only
available on SA11x0.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Nicolas Pitre <nico@marvell.com>

Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

SPIN_LOCK_UNLOCKED is deprecated as lockdep cannot properly work with
locks initialized with it.

This fix is necessary to compile the linux-rt tree for ARM.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Steven Rostedt <srostedt@redhat.com>

In omap24xx_cpu_suspend assembly routine, the r2 register which holds
the address of the SDRC_POWER reg is set to zero before the value is
written back triggering a fault due to writing to address zero.

It's hard to tell where this change was introduced since this file
has been moved and merged.

While this fix prevents a crash, suspend on my n810 is broken with
current kernels.  I never come out of suspend.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

By Ingo Molnar, interrupts are not masked by default.
(refer to 76d21601)

But if interrupts are not masked, the processor can wake up while in
Suspend-to-RAM state by an external interrupt. For example, if an
OMAP3 board is connected to Host PC by USB and entered to Suspend-to-RAM
state, it wake up automatically by M_IRQ_92. The disable_irq() function
can't disable the interrupt in H/W level, So I modified
arch/arm/mach-omap2/irq.c
Signed-off-by: NKim Kyuwon <chammoru@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

When 32 kHz timer is used the min_delta_ns should be initialized so
that it reflects the timer programming cost. A write to the timer
device will be usually posted, but it takes roughly 3 cycles before
it is effective. If the timer is reprogrammed before that, the CPU
will stall until the previous write completes. This was pointed out by
Richard Woodruff.

Since the lower bound for min_delta_ns is 1000, the change is visible
only with tick rates less than 3 MHz.

Also note that the old value is incorrect for 32 kHz also due to
a rounding error, and it can cause the timer queue to hang (due to
clockevent code trying to program the timer with zero ticks).
Signed-off-by: NAaro Koskinen <Aaro.Koskinen@nokia.com>
Reviewed-by: NRichard Woodruff <r-woodruff2@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The naming accidentally broke while changing the name for the
driver to not to conflict with the other mmc driver.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Fix omap34xx revision detection for ES3.1
Signed-off-by: NTony Lindgren <tony@atomide.com>

This has similar symptoms than 66c23551
where just omap_request_dma, omap_dma_link_lch and omap_dma_unlink_lch
can cause incorrect dump_stack(). Here it can happen if channel has been
used before and the channel flags variable holds old status.
Signed-off-by: NJarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

CSR must be cleared before invoking the callback.

If the callback function starts a new, fast DMA transfer on the same
channel, the completion status might lost if CSR is cleared after
the callback invocation.
Signed-off-by: NJuha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>