1. 30 1月, 2015 1 次提交
  2. 28 1月, 2015 4 次提交
    • M
      arm64: mm: use *_sect to check for section maps · a1c76574
      Mark Rutland 提交于
      The {pgd,pud,pmd}_bad family of macros have slightly fuzzy
      cross-architecture semantics, and seem to imply a populated entry that
      is not a next-level table, rather than a particular type of entry (e.g.
      a section map).
      
      In arm64 code, for those cases where we care about whether an entry is a
      section mapping, we can instead use the {pud,pmd}_sect macros to
      explicitly check for this case. This helps to document precisely what we
      care about, making the code easier to read, and allows for future
      relaxation of the *_bad macros to check for other "bad" entries.
      
      To that end this patch updates the table dumping and initial table setup
      to check for section mappings with {pud,pmd}_sect, and adds/restores
      BUG_ON(*_bad((*p)) checks after we've handled the *_sect and *_none
      cases so as to catch remaining "bad" cases.
      
      In the fault handling code, show_pte is left with *_bad checks as it
      only cares about whether it can walk the next level table, and this path
      is used for both kernel and userspace fault handling. The former case
      will be followed by a die() where we'll report the address that
      triggered the fault, which can be useful context for debugging.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NSteve Capper <steve.capper@linaro.org>
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Laura Abbott <lauraa@codeaurora.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      a1c76574
    • M
      arm64: drop unnecessary cache+tlb maintenance · a3bba370
      Mark Rutland 提交于
      In paging_init, we call flush_cache_all, but this is backed by Set/Way
      operations which may not achieve anything in the presence of cache line
      migration and/or system caches. If the caches are already in an
      inconsistent state at this point, there is nothing we can do (short of
      flushing the entire physical address space by VA) to empty architected
      and system caches. As such, flush_cache_all only serves to mask other
      potential bugs. Hence, this patch removes the boot-time call to
      flush_cache_all.
      
      Immediately after the cache maintenance we flush the TLBs, but this is
      also unnecessary. Before enabling the MMU, the TLBs are invalidated, and
      thus are initially clean. When changing the contents of active tables
      (e.g. in fixup_executable() for DEBUG_RODATA) we perform the required
      TLB maintenance following the update, and therefore no additional
      maintenance is required to ensure the new table entries are in effect.
      Since activating the MMU we will not have modified system register
      fields permitted to be cached in a TLB, and therefore do not need
      maintenance for any cached system register fields. Hence, the TLB flush
      is unnecessary.
      
      Shortly after the unnecessary TLB flush, we update TTBR0 to point to an
      empty zero page rather than the idmap, and flush the TLBs. This
      maintenance is necessary to remove the global idmap entries from the
      TLBs (as they would conflict with userspace mappings), and is retained.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Acked-by: NSteve Capper <steve.capper@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      a3bba370
    • Z
      arm64:mm: free the useless initial page table · 523d6e9f
      zhichang.yuan 提交于
      For 64K page system, after mapping a PMD section, the corresponding initial
      page table is not needed any more. That page can be freed.
      Signed-off-by: NZhichang Yuan <zhichang.yuan@linaro.org>
      [catalin.marinas@arm.com: added BUG_ON() to catch late memblock freeing]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      523d6e9f
    • C
      arm64: Enable CPU_IDLE in defconfig · 62fa5e20
      Catalin Marinas 提交于
      This patch enables CPU_IDLE and the generic arm64 cpuidle driver
      (ARM64_CPUIDLE).
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      62fa5e20
  3. 27 1月, 2015 6 次提交
    • L
      arm64: kernel: remove ARM64_CPU_SUSPEND config option · af3cfdbf
      Lorenzo Pieralisi 提交于
      ARM64_CPU_SUSPEND config option was introduced to make code providing
      context save/restore selectable only on platforms requiring power
      management capabilities.
      
      Currently ARM64_CPU_SUSPEND depends on the PM_SLEEP config option which
      in turn is set by the SUSPEND config option.
      
      The introduction of CPU_IDLE for arm64 requires that code configured
      by ARM64_CPU_SUSPEND (context save/restore) should be compiled in
      in order to enable the CPU idle driver to rely on CPU operations
      carrying out context save/restore.
      
      The ARM64_CPUIDLE config option (ARM64 generic idle driver) is therefore
      forced to select ARM64_CPU_SUSPEND, even if there may be (ie PM_SLEEP)
      failed dependencies, which is not a clean way of handling the kernel
      configuration option.
      
      For these reasons, this patch removes the ARM64_CPU_SUSPEND config option
      and makes the context save/restore dependent on CPU_PM, which is selected
      whenever either SUSPEND or CPU_IDLE are configured, cleaning up dependencies
      in the process.
      
      This way, code previously configured through ARM64_CPU_SUSPEND is
      compiled in whenever a power management subsystem requires it to be
      present in the kernel (SUSPEND || CPU_IDLE), which is the behaviour
      expected on ARM64 kernels.
      
      The cpu_suspend and cpu_init_idle CPU operations are added only if
      CPU_IDLE is selected, since they are CPU_IDLE specific methods and
      should be grouped and defined accordingly.
      
      PSCI CPU operations are updated to reflect the introduced changes.
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      af3cfdbf
    • M
      arm64: make sys_call_table const · c623b33b
      Mark Rutland 提交于
      As with x86, mark the sys_call_table const such that it will be placed
      in the .rodata section. This will cause attempts to modify the table
      (accidental or deliberate) to fail when strict page permissions are in
      place. In the absence of strict page permissions, there should be no
      functional change.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      c623b33b
    • C
      arm64: Remove asm/syscalls.h · 96486069
      Catalin Marinas 提交于
      This patch moves the sys_rt_sigreturn_wrapper prototype to
      arch/arm64/kernel/sys.c and removes the asm/syscalls.h header.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      96486069
    • C
      arm64: Implement the compat_sys_call_table in C · 0156411b
      Catalin Marinas 提交于
      Unlike the sys_call_table[], the compat one was implemented in sys32.S
      making it impossible to notice discrepancies between the number of
      compat syscalls and the __NR_compat_syscalls macro, the latter having to
      be defined in asm/unistd.h as including asm/unistd32.h would cause
      conflicts on __NR_* definitions. With this patch, incorrect
      __NR_compat_syscalls values will result in a build-time error.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Suggested-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      0156411b
    • C
      syscalls: Declare sys_*stat64 prototypes if __ARCH_WANT_(COMPAT_)STAT64 · 54e45c16
      Catalin Marinas 提交于
      Currently, the sys_stat64, sys_fstat64 and sys_lstat64 prototpyes are
      only declared if BITS_PER_LONG == 32. Following commit 0753f70f
      (fs: Build sys_stat64() and friends if __ARCH_WANT_COMPAT_STAT64), the
      implementation of these functions is allowed on 64-bit systems for
      compat support. The patch changes the condition on the prototype
      declaration from BITS_PER_LONG == 32 to defined(__ARCH_WANT_STAT64) ||
      defined(__ARCH_WANT_COMPAT_STAT64).
      
      In addition, it moves the sys_fstatat64 prototype under the same #if
      block
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NAndrew Morton <akpm@linux-foundation.org>
      Cc: Arnd Bergmann <arnd@arndb.de>
      54e45c16
    • C
      compat: Declare compat_sys_sigpending and compat_sys_sigprocmask prototypes · e9fb8b7e
      Catalin Marinas 提交于
      __ARCH_WANT_SYS_SIGPENDING or __ARCH_WANT_SYS_SIGPROGMASK may be defined
      for compat support but the corresponding prototypes are missing from
      linux/compat.h.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NAndrew Morton <akpm@linux-foundation.org>
      Cc: Arnd Bergmann <arnd@arndb.de>
      e9fb8b7e
  4. 24 1月, 2015 7 次提交
  5. 23 1月, 2015 4 次提交
    • S
      arm64: Fix SCTLR_EL1 initialisation · 9f71ac96
      Suzuki K. Poulose 提交于
      We initialise the SCTLR_EL1 value by read-modify-writeback
      of the desired bits, leaving the other bits (including reserved
      bits(RESx)) untouched. However, sometimes the boot monitor could
      leave garbage values in the RESx bits which could have different
      implications. This patch makes sure that all the bits, including
      the RESx bits, are set to the proper state, except for the
      'endianness' control bits, EE(25) & E0E(24)- which are set early
      in the el2_setup.
      
      Updated the state of the Bit[6] in the comment to RES0 in the
      comment.
      Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      9f71ac96
    • M
      arm64: add ioremap physical address information · da1f2b82
      Min-Hua Chen 提交于
      In /proc/vmallocinfo, it's good to show the physical address
      of each ioremap in vmallocinfo. Add physical address information
      in arm64 ioremap.
      
      0xffffc900047f2000-0xffffc900047f4000    8192 _nv013519rm+0x57/0xa0
      [nvidia] phys=f8100000 ioremap
      0xffffc900047f4000-0xffffc900047f6000    8192 _nv013519rm+0x57/0xa0
      [nvidia] phys=f8008000 ioremap
      0xffffc90004800000-0xffffc90004821000  135168 e1000_probe+0x22c/0xb95
      [e1000e] phys=f4300000 ioremap
      0xffffc900049c0000-0xffffc900049e1000  135168 _nv013521rm+0x4d/0xd0
      [nvidia] phys=e0140000 ioremap
      Signed-off-by: NMin-Hua Chen <orca.chen@gmail.com>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      da1f2b82
    • M
      arm64: mm: dump: add missing includes · 764011ca
      Mark Rutland 提交于
      The arm64 dump code is currently relying on some definitions which are
      pulled in via transitive dependencies. It seems we have implicit
      dependencies on the following definitions:
      
      * MODULES_VADDR         (asm/memory.h)
      * MODULES_END           (asm/memory.h)
      * PAGE_OFFSET           (asm/memory.h)
      * PTE_*                 (asm/pgtable-hwdef.h)
      * ENOMEM                (linux/errno.h)
      * device_initcall       (linux/init.h)
      
      This patch ensures we explicitly include the relevant headers for the
      above items, fixing the observed build issue and hopefully preventing
      future issues as headers are refactored.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reported-by: NMark Brown <broonie@kernel.org>
      Acked-by: NSteve Capper <steve.capper@linaro.org>
      Cc: Laura Abbott <lauraa@codeaurora.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      764011ca
    • M
      arm64: Fix overlapping VA allocations · aa03c428
      Mark Rutland 提交于
      PCI IO space was intended to be 16MiB, at 32MiB below MODULES_VADDR, but
      commit d1e6dc91 ("arm64: Add architectural support for PCI")
      extended this to cover the full 32MiB. The final 8KiB of this 32MiB is
      also allocated for the fixmap, allowing for potential clashes between
      the two.
      
      This change was masked by assumptions in mem_init and the page table
      dumping code, which assumed the I/O space to be 16MiB long through
      seaparte hard-coded definitions.
      
      This patch changes the definition of the PCI I/O space allocation to
      live in asm/memory.h, along with the other VA space allocations. As the
      fixmap allocation depends on the number of fixmap entries, this is moved
      below the PCI I/O space allocation. Both the fixmap and PCI I/O space
      are guarded with 2MB of padding. Sites assuming the I/O space was 16MiB
      are moved over use new PCI_IO_{START,END} definitions, which will keep
      in sync with the size of the IO space (now restored to 16MiB).
      
      As a useful side effect, the use of the new PCI_IO_{START,END}
      definitions prevents a build issue in the dumping code due to a (now
      redundant) missing include of io.h for PCI_IOBASE.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Laura Abbott <lauraa@codeaurora.org>
      Cc: Liviu Dudau <liviu.dudau@arm.com>
      Cc: Steve Capper <steve.capper@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      [catalin.marinas@arm.com: reorder FIXADDR and PCI_IO address_markers_idx enum]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      aa03c428
  6. 22 1月, 2015 3 次提交
  7. 17 1月, 2015 2 次提交
  8. 15 1月, 2015 10 次提交
    • K
      arm64: kill off the libgcc dependency · d67703a8
      Kevin Hao 提交于
      The arm64 kernel builds fine without the libgcc. Actually it should not
      be used at all in the kernel. The following are the reasons indicated
      by Russell King:
      
        Although libgcc is part of the compiler, libgcc is built with the
        expectation that it will be running in userland - it expects to link
        to a libc.  That's why you can't build libgcc without having the glibc
        headers around.
      
        [...]
      
        Meanwhile, having the kernel build the compiler support functions that
        it needs ensures that (a) we know what compiler support functions are
        being used, (b) we know the implementation of those support functions
        are sane for use in the kernel, (c) we can build them with appropriate
        compiler flags for best performance, and (d) we remove an unnecessary
        dependency on the build toolchain.
      Signed-off-by: NKevin Hao <haokexin@gmail.com>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      d67703a8
    • C
      Merge branch 'arm64/common-esr-macros' of git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux · 0ce339a9
      Catalin Marinas 提交于
      ESR_ELx definitions clean-up from Mark Rutland.
      
      * 'arm64/common-esr-macros' of git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux:
        arm64: kvm: decode ESR_ELx.EC when reporting exceptions
        arm64: kvm: remove ESR_EL2_* macros
        arm64: remove ESR_EL1_* macros
        arm64: kvm: move to ESR_ELx macros
        arm64: decode ESR_ELx.EC when reporting exceptions
        arm64: move to ESR_ELx macros
        arm64: introduce common ESR_ELx_* definitions
      0ce339a9
    • M
      arm64: kvm: decode ESR_ELx.EC when reporting exceptions · 056bb5f5
      Mark Rutland 提交于
      To aid the developer when something triggers an unexpected exception,
      decode the ESR_ELx.EC field when logging an ESR_ELx value using the
      newly introduced esr_get_class_string. This doesn't tell the developer
      the specifics of the exception encoded in the remaining IL and ISS bits,
      but it can be helpful to distinguish between exception classes (e.g.
      SError and a data abort) without having to manually decode the field,
      which can be tiresome.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      056bb5f5
    • M
      arm64: kvm: remove ESR_EL2_* macros · 6e53031e
      Mark Rutland 提交于
      Now that all users have been moved over to the common ESR_ELx_* macros,
      remove the redundant ESR_EL2 macros. To maintain compatibility with the
      fault handling code shared with 32-bit, the FSC_{FAULT,PERM} macros are
      retained as aliases for the common ESR_ELx_FSC_{FAULT,PERM} definitions.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      6e53031e
    • M
      arm64: remove ESR_EL1_* macros · 4a939087
      Mark Rutland 提交于
      Now that all users have been moved over to the common ESR_ELx_* macros,
      remove the redundant ESR_EL1 macros.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      4a939087
    • M
      arm64: kvm: move to ESR_ELx macros · c6d01a94
      Mark Rutland 提交于
      Now that we have common ESR_ELx macros, make use of them in the arm64
      KVM code. The addition of <asm/esr.h> to the include path highlighted
      badly ordered (i.e. not alphabetical) include lists; these are changed
      to alphabetical order.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      c6d01a94
    • M
      arm64: decode ESR_ELx.EC when reporting exceptions · 60a1f02c
      Mark Rutland 提交于
      To aid the developer when something triggers an unexpected exception,
      decode the ESR_ELx.EC field when logging an ESR_ELx value. This doesn't
      tell the developer the specifics of the exception encoded in the
      remaining IL and ISS bits, but it can be helpful to distinguish between
      exception classes (e.g. SError and a data abort) without having to
      manually decode the field, which can be tiresome.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      60a1f02c
    • M
      arm64: move to ESR_ELx macros · aed40e01
      Mark Rutland 提交于
      Now that we have common ESR_ELx_* macros, move the core arm64 code over
      to them.
      
      There should be no functional change as a result of this patch.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      aed40e01
    • M
      arm64: introduce common ESR_ELx_* definitions · cf99a48d
      Mark Rutland 提交于
      Currently we have separate ESR_EL{1,2}_* macros, despite the fact that
      the encodings are common. While encodings are architected to refer to
      the current EL or a lower EL, the macros refer to particular ELs (e.g.
      ESR_ELx_EC_DABT_EL0). Having these duplicate definitions is redundant,
      and their naming is misleading.
      
      This patch introduces common ESR_ELx_* macros that can be used in all
      cases, in preparation for later patches which will migrate existing
      users over. Some additional cleanups are made in the process:
      
      * Suffixes for particular exception levelts (e.g. _EL0, _EL1) are
        replaced with more general _LOW and _CUR suffixes, matching the
        architectural intent.
      
      * ESR_ELx_EC_WFx, rather than ESR_ELx_EC_WFI is introduced, as this
        EC encoding covers traps from both WFE and WFI. Similarly,
        ESR_ELx_WFx_ISS_WFE rather than ESR_ELx_EC_WFI_ISS_WFE is introduced.
      
      * Multi-bit fields are given consistently named _SHIFT and _MASK macros.
      
      * UL() is used for compatiblity with assembly files.
      
      * Comments are added for currently unallocated ESR_ELx.EC encodings.
      
      For fields other than ESR_ELx.EC, macros are only implemented for fields
      for which there is already an ESR_EL{1,2}_* macro.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
      cf99a48d
    • S
      arm64: kernel: add support for cpu cache information · 5d425c18
      Sudeep Holla 提交于
      This patch adds support for cacheinfo on ARM64.
      
      On ARMv8, the cache hierarchy can be identified through Cache Level ID
      (CLIDR) register while the cache geometry is provided by Cache Size ID
      (CCSIDR) register.
      
      Since the architecture doesn't provide any way of detecting the cpus
      sharing particular cache, device tree is used for the same purpose.
      Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      5d425c18
  9. 14 1月, 2015 2 次提交
    • M
      arm64: remove broken cachepolicy code · 26a945ca
      Mark Rutland 提交于
      The cachepolicy kernel parameter was intended to aid in the debugging of
      coherency issues, but it is fundamentally broken for several reasons:
      
       * On SMP platforms, only the boot CPU's tcr_el1 is altered. Secondary
         CPUs may therefore use differ w.r.t. the attributes they apply to
         MT_NORMAL memory, resulting in a loss of coherency.
      
       * The cache maintenance using flush_dcache_all (based on Set/Way
         operations) is not guaranteed to empty a given CPU's cache hierarchy
         while said CPU has caches enabled, it cannot empty the caches of
         other coherent PEs, nor is it guaranteed to flush data to the PoC
         even when caches are disabled.
      
       * The TLBs are not invalidated around the modification of MAIR_EL1 and
         TCR_EL1, as required by the architecture (as both are permitted to be
         cached in a TLB). This may result in CPUs using attributes other than
         those expected for some memory accesses, resulting in a loss of
         coherency.
      
       * Exclusive accesses are not architecturally guaranteed to function as
         expected on memory marked as Write-Through or Non-Cacheable. Thus
         changing the attributes of MT_NORMAL away from the (architecurally
         safe) defaults may cause uses of these instructions (e.g. atomics) to
         behave erratically.
      
      Given this, the cachepolicy code cannot be used for debugging purposes
      as it alone is likely to cause coherency issues. This patch removes the
      broken cachepolicy code.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      26a945ca
    • C
      Merge tag 'for-3.20' of http://git.linaro.org/people/ard.biesheuvel/linux-arm into upstream · c26a535b
      Catalin Marinas 提交于
      UEFI updates for arm64
      
      This series consists of a reimplementation of the virtual remapping of
      UEFI Runtime Services in a way that is stable across kexec, including
      the required preparatory refactoring and other work to set the stage,
      and some cleaning up afterwards to remove boot services memory and
      identitity map handling that has now become redundant.
      
      * tag 'for-3.20' of http://git.linaro.org/people/ard.biesheuvel/linux-arm:
        arm64/efi: remove idmap manipulations from UEFI code
        arm64/efi: remove free_boot_services() and friends
        arm64/efi: move SetVirtualAddressMap() to UEFI stub
        arm64/efi: set EFI_ALLOC_ALIGN to 64 KB
        efi: efistub: allow allocation alignment larger than EFI_PAGE_SIZE
        efi: split off remapping code from efi_config_init()
        arm64/mm: add create_pgd_mapping() to create private page tables
        arm64/mm: add explicit struct_mm argument to __create_mapping()
      c26a535b
  10. 13 1月, 2015 1 次提交