- 25 7月, 2015 1 次提交
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由 Russell King 提交于
The existing memory barrier macro causes a significant amount of code to be inserted inline at every call site. For example, in gpio_set_irq_type(), we have this for mb(): c0344c08: f57ff04e dsb st c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230> c0344c10: e3590004 cmp r9, #4 c0344c14: e5983014 ldr r3, [r8, #20] c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc> c0344c1c: e3530000 cmp r3, #0 c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4> c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc c0344c2c: e12fff33 blx r3 c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0 c0344c38: e5963004 ldr r3, [r6, #4] Moving the outer_cache_sync() call out of line reduces the impact of the barrier: c0344968: f57ff04e dsb st c034496c: e35a0004 cmp sl, #4 c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8> c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb> c034497c: e5953004 ldr r3, [r5, #4] This should reduce the cache footprint of this code. Overall, this results in a reduction of around 20K in the kernel size: text data bss dec hex filename 10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old 10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new Another advantage to this approach is that we can finally resolve the issue of SoCs which have their own memory barrier requirements within multiplatform kernels (such as OMAP.) Here, the bus interconnects need additional handling to ensure that writes become visible in the correct order (eg, between dma_map() operations, writes to DMA coherent memory, and MMIO accesses.) Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NRichard Woodruff <r-woodruff2@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 5月, 2015 1 次提交
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由 Linus Walleij 提交于
The l2x0 level 2 cache initialization used a static map to get at the l2x0 registers. Get rid of this by getting the register range from the device tree and just remap it for the short time we need it. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 7月, 2014 1 次提交
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由 Linus Walleij 提交于
This cleans out non-DT cache setup (the ux500 is DT only), and sinks the l2cc base into the unlock function. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 30 5月, 2014 4 次提交
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由 Russell King 提交于
ux500 can't change the auxiliary control register, so there's no point passing values to try and modify it to the l2x0 init functions. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
ux500 can't write to any of the secure registers on the L2C controllers, so provide a dummy handler which ignores all writes. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 9月, 2013 1 次提交
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由 Linus Walleij 提交于
This fixes a multiplatform regression on the Ux500. When compiling the Ux500 platforms in multiplatform configurations both PL310_ERRATA_588369 and PL310_ERRATA_727915 would crash the platform when trying to launch the init process. The Ux500 cannot access the debug registers of the PL310, it will just crash if you try this. So disable this by setting the debug callback to NULL when initializing the l2x0 on this platform. Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 27 6月, 2013 1 次提交
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由 Linus Walleij 提交于
This makes the l2x0 initialization fail gracefully on non-ux500 systems. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 08 4月, 2013 1 次提交
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由 Linus Walleij 提交于
This removes <mach/hardware.h> and <mach/db8500-regs.h> from the Ux500, merging them into the local include "db8500-regs.h" in mach-ux500. There is some impact outside the ux500 machine, but most of it is dealt with in earlier patches. Contains portions of a clean-up patch from Arnd Bergmann. Cc: Samuel Ortiz <sameo@linux.intel.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 3月, 2013 1 次提交
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由 Maxime Coquelin 提交于
DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540. Fix this by modifying ux500_l2x0_init() to use 128KB way size for all cpus in the x540 family. Signed-off-by: NMaxime Coquelin <maxime.coquelin@stericsson.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NFabio Baltieri <fabio.baltieri@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 30 1月, 2013 1 次提交
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由 Linus Walleij 提交于
This removes the file <mach/id.h> from the global kernel include scope, making it a pure mach-ux500 detail. All ASIC specifics needed by drivers shall henceforth be passed from either platform data or the device tree. Cc: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: NSamuel Ortiz <sameo@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 09 8月, 2012 1 次提交
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由 Linus Walleij 提交于
Counting the U9540 and the new U8540 as a U8500 family member does not work. Instead, split the function in two: cpu_is_u8500_family() covering U8500 and U8520 cpu_is_ux540_family() covering U9540 and U8540 This works much better in practice. Update users to keep the same behaviour. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 02 5月, 2012 2 次提交
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由 Linus Walleij 提交于
This platform has been obsoleted and was only available inside of ST-Ericsson, no users of this code are left in the world. This deletes the core U5500 support entirely in the same manner as the obsoleted U8500 silicon was previously deleted. The cpu_is_u5500() macros that can read out the CPU ID is left until the next kernel cycle, this makes it possible to merge deletion of dependent drivers without breakage. This also has the upside of removing the mailbox driver which was our only driver that was outside the drivers/* hiearchy, now the machine directory only handles machines and nothing else. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Jonas Aberg <jonas.aberg@stericsson.com> Cc: Per Forlin <per.forlin@stericsson.com> Cc: Ulf Hansson <ulf.hansson@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This adds support for the U9540 variant of the U8500 series. This is an application processor without internal modem. This is the most basic part with ASIC ID, CPU-related fixes, IRQ list, register ranges, timer, UART, and L2 cache setup. This is based on a patch by Michel Jaouen which was rewritten to fit with the latest 3.3 kernel. ChangeLog v1->v2: deleted the irqs-db9540.h file since we expect to migrate to using Device Tree for getting the IRQs to devices. ChangeLog v2->v3: introduced a fixed virtual offset for the ROM as suggested by Arnd Bergmann. Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NSebastien Pasdeloup <sebastien.pasdeloup-nonst@stericsson.com> Signed-off-by: NMichel Jaouen <michel.jaouen@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 17 3月, 2012 1 次提交
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由 Lee Jones 提交于
This provides PL310 Level 2 Cache Controller Device Tree support for all u8500 based devices. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 20 1月, 2012 1 次提交
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由 srinidhi kasagar 提交于
Invalidating outer cache without disabling it is a big nono, and so, remove the machine specific outer.inv_all And at the same time it does not prevent us overriding outer.disable as we do not have any such secure SMI to handle the same while kexec disables the outer cache. Signed-off-by: NSrinidhi Kasagar <srinidhi.kasagar@stericsson.com> Reviewed-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 30 8月, 2011 1 次提交
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由 Linus Walleij 提交于
Following mach-imx we break out the l2x0 handling into its own file, avoiding some ifdefs. Also remove unnecessary creation of local pointers when there is already one file-local readily available. Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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