1. 03 5月, 2012 5 次提交
  2. 21 3月, 2012 1 次提交
    • A
      drm/radeon/kms: add support for the CONST IB to the CS ioctl · dfcf5f36
      Alex Deucher 提交于
      This adds a new chunk id to the CS ioctl to support the
      INDIRECT_BUFFER_CONST packet.
      
      On SI, the CP adds a new engine called the CE (Constant Engine)
      which runs simulatenously with the DE (Drawing Engine, formerly
      called the ME).  This allows the CP to process two related IBs
      simultaneously.  The CE is tasked with loading the constant data
      (constant buffers, resource descriptors, samplers, etc.) while
      the DE loads context register state and issues drawing commands.
      It's up to the userspace application to sychronize the CE and the
      DE using special synchronization packets.
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      dfcf5f36
  3. 29 2月, 2012 1 次提交
  4. 22 2月, 2012 1 次提交
  5. 25 1月, 2012 2 次提交
  6. 06 1月, 2012 1 次提交
    • J
      drm/radeon: GPU virtual memory support v22 · 721604a1
      Jerome Glisse 提交于
      Virtual address space are per drm client (opener of /dev/drm).
      Client are in charge of virtual address space, they need to
      map bo into it by calling DRM_RADEON_GEM_VA ioctl.
      
      First 16M of virtual address space is reserved by the kernel.
      
      Once using 2 level page table we should be able to have a small
      vram memory footprint for each pt (there would be one pt for all
      gart, one for all vram and then one first level for each virtual
      address space).
      
      Plan include using the sub allocator for a common vm page table
      area and using memcpy to copy vm page table in & out. Or use
      a gart object and copy things in & out using dma.
      
      v2: agd5f fixes:
      - Add vram base offset for vram pages.  The GPU physical address of a
      vram page is FB_OFFSET + page offset.  FB_OFFSET is 0 on discrete
      cards and the physical bus address of the stolen memory on
      integrated chips.
      - VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
      
      v3: agd5f:
      - integrate with the semaphore/multi-ring stuff
      
      v4:
      - rebase on top ttm dma & multi-ring stuff
      - userspace is now in charge of the address space
      - no more specific cs vm ioctl, instead cs ioctl has a new
        chunk
      
      v5:
      - properly handle mem == NULL case from move_notify callback
      - fix the vm cleanup path
      
      v6:
      - fix update of page table to only happen on valid mem placement
      
      v7:
      - add tlb flush for each vm context
      - add flags to define mapping property (readable, writeable, snooped)
      - make ring id implicit from ib->fence->ring, up to each asic callback
        to then do ring specific scheduling if vm ib scheduling function
      
      v8:
      - add query for ib limit and kernel reserved virtual space
      - rename vm->size to max_pfn (maximum number of page)
      - update gem_va ioctl to also allow unmap operation
      - bump kernel version to allow userspace to query for vm support
      
      v9:
      - rebuild page table only when bind and incrementaly depending
        on bo referenced by cs and that have been moved
      - allow virtual address space to grow
      - use sa allocator for vram page table
      - return invalid when querying vm limit on non cayman GPU
      - dump vm fault register on lockup
      
      v10: agd5f:
      - Move the vm schedule_ib callback to a standalone function, remove
        the callback and use the existing ib_execute callback for VM IBs.
      
      v11:
      - rebase on top of lastest Linus
      
      v12: agd5f:
      - remove spurious backslash
      - set IB vm_id to 0 in radeon_ib_get()
      
      v13: agd5f:
      - fix handling of RADEON_CHUNK_ID_FLAGS
      
      v14:
      - fix va destruction
      - fix suspend resume
      - forbid bo to have several different va in same vm
      
      v15:
      - rebase
      
      v16:
      - cleanup left over of vm init/fini
      
      v17: agd5f:
      - cs checker
      
      v18: agd5f:
      - reworks the CS ioctl to better support multiple rings and
      VM.  Rather than adding a new chunk id for VM, just re-use the
      IB chunk id and add a new flags for VM mode.  Also define additional
      dwords for the flags chunk id to define the what ring we want to use
      (gfx, compute, uvd, etc.) and the priority.
      
      v19:
      - fix cs fini in weird case of no ib
      - semi working flush fix for ni
      - rebase on top of sa allocator changes
      
      v20: agd5f:
      - further CS ioctl cleanups from Christian's comments
      
      v21: agd5f:
      - integrate CS checker improvements
      
      v22: agd5f:
      - final cleanups for release, only allow VM CS on cayman
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      721604a1
  7. 05 1月, 2012 2 次提交
  8. 21 12月, 2011 10 次提交
  9. 18 10月, 2011 1 次提交
  10. 10 4月, 2011 1 次提交
  11. 09 4月, 2011 1 次提交
  12. 23 2月, 2011 1 次提交
  13. 17 2月, 2011 1 次提交
  14. 18 11月, 2010 1 次提交
  15. 06 10月, 2010 1 次提交
    • A
      drm/radeon/kms: enable writeback (v2) · 724c80e1
      Alex Deucher 提交于
      When writeback is enabled, the GPU shadows writes to certain
      registers into a buffer in memory.  The driver can then read
      the values from the shadow rather than reading back from the
      register across the bus.  Writeback can be disabled by setting
      the no_wb module param to 1.
      
      On r6xx/r7xx/evergreen, the following registers are shadowed:
      - CP scratch registers
      - CP read pointer
      - IH write pointer
      On r1xx-rr5xx, the following registers are shadowed:
      - CP scratch registers
      - CP read pointer
      
      v2:
      - Combine wb patches for r6xx-evergreen and r1xx-r5xx
      - Writeback is disabled on AGP boards since it tends to be
      unreliable on AGP using the gart.
      - Check radeon_wb_init return values properly.
      Signed-off-by: NAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      724c80e1
  16. 18 5月, 2010 2 次提交
  17. 30 3月, 2010 1 次提交
    • T
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking... · 5a0e3ad6
      Tejun Heo 提交于
      include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
      
      percpu.h is included by sched.h and module.h and thus ends up being
      included when building most .c files.  percpu.h includes slab.h which
      in turn includes gfp.h making everything defined by the two files
      universally available and complicating inclusion dependencies.
      
      percpu.h -> slab.h dependency is about to be removed.  Prepare for
      this change by updating users of gfp and slab facilities include those
      headers directly instead of assuming availability.  As this conversion
      needs to touch large number of source files, the following script is
      used as the basis of conversion.
      
        http://userweb.kernel.org/~tj/misc/slabh-sweep.py
      
      The script does the followings.
      
      * Scan files for gfp and slab usages and update includes such that
        only the necessary includes are there.  ie. if only gfp is used,
        gfp.h, if slab is used, slab.h.
      
      * When the script inserts a new include, it looks at the include
        blocks and try to put the new include such that its order conforms
        to its surrounding.  It's put in the include block which contains
        core kernel includes, in the same order that the rest are ordered -
        alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
        doesn't seem to be any matching order.
      
      * If the script can't find a place to put a new include (mostly
        because the file doesn't have fitting include block), it prints out
        an error message indicating which .h file needs to be added to the
        file.
      
      The conversion was done in the following steps.
      
      1. The initial automatic conversion of all .c files updated slightly
         over 4000 files, deleting around 700 includes and adding ~480 gfp.h
         and ~3000 slab.h inclusions.  The script emitted errors for ~400
         files.
      
      2. Each error was manually checked.  Some didn't need the inclusion,
         some needed manual addition while adding it to implementation .h or
         embedding .c file was more appropriate for others.  This step added
         inclusions to around 150 files.
      
      3. The script was run again and the output was compared to the edits
         from #2 to make sure no file was left behind.
      
      4. Several build tests were done and a couple of problems were fixed.
         e.g. lib/decompress_*.c used malloc/free() wrappers around slab
         APIs requiring slab.h to be added manually.
      
      5. The script was run on all .h files but without automatically
         editing them as sprinkling gfp.h and slab.h inclusions around .h
         files could easily lead to inclusion dependency hell.  Most gfp.h
         inclusion directives were ignored as stuff from gfp.h was usually
         wildly available and often used in preprocessor macros.  Each
         slab.h inclusion directive was examined and added manually as
         necessary.
      
      6. percpu.h was updated not to include slab.h.
      
      7. Build test were done on the following configurations and failures
         were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
         distributed build env didn't work with gcov compiles) and a few
         more options had to be turned off depending on archs to make things
         build (like ipr on powerpc/64 which failed due to missing writeq).
      
         * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
         * powerpc and powerpc64 SMP allmodconfig
         * sparc and sparc64 SMP allmodconfig
         * ia64 SMP allmodconfig
         * s390 SMP allmodconfig
         * alpha SMP allmodconfig
         * um on x86_64 SMP allmodconfig
      
      8. percpu.h modifications were reverted so that it could be applied as
         a separate patch and serve as bisection point.
      
      Given the fact that I had only a couple of failures from tests on step
      6, I'm fairly confident about the coverage of this conversion patch.
      If there is a breakage, it's likely to be something in one of the arch
      headers which should be easily discoverable easily on most builds of
      the specific arch.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
      5a0e3ad6
  18. 20 2月, 2010 1 次提交
  19. 18 2月, 2010 1 次提交
    • J
      drm/radeon/kms: fix indirect buffer management V2 · 91cb91be
      Jerome Glisse 提交于
      There is 3 different distinct states for an indirect buffer (IB) :
        1- free with no fence
        2- free with a fence
        3- non free (fence doesn't matter)
      Previous code mixed case 2 & 3 in a single one leading to possible
      catastrophique failure. This patch rework the handling and properly
      separate each case. So when you get ib we set the ib as non free and
      fence status doesn't matter. Fence become active (ie has a meaning
      for the ib code) once the ib is scheduled or free. This patch also
      get rid of the alloc bitmap as it was overkill, we know go through
      IB pool list like in a ring buffer as the oldest IB is the first
      one the will be free.
      
      Fix :
      https://bugs.freedesktop.org/show_bug.cgi?id=26438
      and likely other bugs.
      
      V2 remove the scheduled list, it's useless now, fix free ib scanning
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      91cb91be
  20. 16 2月, 2010 1 次提交
    • J
      drm/radeon/kms: fix indirect buffer management V2 · e821767b
      Jerome Glisse 提交于
      There is 3 different distinct states for an indirect buffer (IB) :
        1- free with no fence
        2- free with a fence
        3- non free (fence doesn't matter)
      Previous code mixed case 2 & 3 in a single one leading to possible
      catastrophique failure. This patch rework the handling and properly
      separate each case. So when you get ib we set the ib as non free and
      fence status doesn't matter. Fence become active (ie has a meaning
      for the ib code) once the ib is scheduled or free. This patch also
      get rid of the alloc bitmap as it was overkill, we know go through
      IB pool list like in a ring buffer as the oldest IB is the first
      one the will be free.
      
      Fix :
      https://bugs.freedesktop.org/show_bug.cgi?id=26438
      and likely other bugs.
      
      V2 remove the scheduled list, it's useless now, fix free ib scanning
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      e821767b
  21. 09 2月, 2010 1 次提交
  22. 02 12月, 2009 1 次提交
    • J
      drm/radeon/kms: Rework radeon object handling · 4c788679
      Jerome Glisse 提交于
      The locking & protection of radeon object was somewhat messy.
      This patch completely rework it to now use ttm reserve as a
      protection for the radeon object structure member. It also
      shrink down the various radeon object structure by removing
      field which were redondant with the ttm information. Last it
      converts few simple functions to inline which should with
      performances.
      
      airlied: rebase on top of r600 and other changes.
      Signed-off-by: NJerome Glisse <jglisse@redhat.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      4c788679
  23. 16 9月, 2009 1 次提交
  24. 14 9月, 2009 1 次提交