- 19 5月, 2018 40 次提交
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由 Anthony Koo 提交于
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nikola Cornij 提交于
Also print HUBP info only if pipe enabled. This fixes having different DTN logs for different test sequences. Signed-off-by: NNikola Cornij <nikola.cornij@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yue Hin Lau 提交于
Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xingyue Tao 提交于
- Adds int max_downscale_src_width in dc struct - Checks and does not support if downscale size is more than 4k (width > 3840) Signed-off-by: NXingyue Tao <xingyue.tao@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Bernstein 提交于
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Charlene Liu 提交于
[Description] for any reason, if driver detects HUBP underflow, if a debug option enabled to enable recovery. it will kick in a sequence of recovery. Signed-off-by: NCharlene Liu <charlene.liu@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
Remove dependency on the old FREESYNC_SW_STATS log mask used by DAL2 Also rename from profiling to displaystats Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
32.32 is redundant, 31.32 does everything we use 32.32 for Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Take the encode rings into account in the idle work handler. Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Take the encode rings into account in the idle work handler. v2: fix typo: s/num_uvd_inst/num_enc_rings/ Reviewed-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Current multi-UVD hardware uses a single clock and power source so handle all instances in the idle handler. Reviewed-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nayan Deshmukh 提交于
That got missed while moving the files outside of amdgpu. Signed-off-by: NNayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tom St Denis 提交于
NFC just comments. (v2): Updated based on feedback from Alex Deucher. Signed-off-by: NTom St Denis <tom.stdenis@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dan Carpenter 提交于
We added some more lines of code to this if statement but forgot to add curly braces. Fixes: 0c24e7ef ("drm/amd/powerplay: add specific changes for VEGAM in smu7_hwmgr.c") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
- Remove unused ASICREV_IS_VEGA12_p() macro - Fix ASICREV_IS_VEGA12_P() macro to properly check against vega20 Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Leftover from bringup. No need to keep it around for upstream. Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Leftover from bringup. No need to keep it around for upstream. Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Reviewed-by: NMichel Dänzer <michel.daenzer@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Andrey Grodzovsky 提交于
This spinlock is superfluous, any call to drm_sched_entity_push_job should already be under a lock together with matching drm_sched_job_init to match the order of insertion into queue with job's fence seqence number. v2: Improve patch description. Add functions documentation describing the locking considerations Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: NChunming Zhou <david1.zhou@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Christian König 提交于
This lock isn't used any more. Signed-off-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NChunming Zhou <david1.zhou@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rex Zhu 提交于
Screen flickering observed while running 1080p video using MPV_VAAPI/VDPAU with 4x4K@60 monitors Need to set higher mclk in this configuration. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Andrey Grodzovsky 提交于
Following change 75fbed20 we never initialize or use the GPU scheduler for KIQ and hence we need to skip KIQ ring when iterating amdgpu_ctx's scheduler entites. Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Must set amdgpu.exp_hw_support=1 on the kernel command line in grub to enable support. Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Feifei Xu 提交于
Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NFeifei Xu <Feifei.Xu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Feifei Xu 提交于
v2: fix whitespace (Alex) Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NFeifei Xu <Feifei.Xu@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Feifei Xu 提交于
New df helpers for 3.6. v2: switch to using df 3.6 headers (Alex) Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NFeifei Xu <Feifei.Xu@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Needed for vega20. Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD instance presents. there is two rings for uvd decode, and 4 rings for uvd encode. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
For Vega20, the 2nd instance uvd IRQ using different client id. Enable the 2nd instance IRQ for uvd 7.2 Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
For Vega20, there are two UVD hardware. Need add the 2nd IH client ID for the 2nd UVD Hardware. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
For Vega20, set num of uvd instance to 2, to enble 2nd instance. The IB test build-in registers need update for vega20 2nd instance. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
For Vega20, there are two UVD Hardware. One more UVD hardware adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS need increase by 3. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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